公开(公告)号：US09461679B2

公开(公告)日：2016-10-04

申请号：US14689036

申请日：2015-04-16

Applicant: BROADCOM CORPORATION

Inventor： Davide Guermandi ,  Silvian Spiridon ,  Dongsoo Daniel Koh ,  Stefano Bozzola ,  Han Yan ,  Mattia Introini ,  Tao Wu

IPC: H04B1/10 ,  H04B1/00 ,  H03F1/32 ,  H03F3/45

CPC classification number: H04B1/10 ,  H03F1/32 ,  H03F3/45475 ,  H03F2200/336 ,  H03F2200/411 ,  H03F2203/45212 ,  H03F2203/45528 ,  H03F2203/45591 ,  H03F2203/45594 ,  H03F2203/45616 ,  H03G1/0088 ,  H04B1/0017

Abstract: A device includes circuitry configured to receive a signal burst, apply one or more filters to the signal burst based to achieve a predetermined image rejection rate, apply at least one harmonic rejection mode to the signal burst, and amplify the signal burst based on a gain partitioning determination.

Abstract translation: 一种设备包括被配置为接收信号脉冲串的电路，基于信号脉冲串施加一个或多个滤波器以实现预定的图像抑制率，对信号脉冲串施加至少一个谐波抑制模式，并且基于增益放大信号脉冲串 划分确定。

公开(公告)号：US20150303954A1

公开(公告)日：2015-10-22

申请号：US14689036

申请日：2015-04-16

Applicant: BROADCOM CORPORATION

Inventor： Davide Guermandi ,  Silvian Spiridon ,  Dongsoo Daniel Koh ,  Stefano Bozzola ,  Han Yan ,  Mattia Introini ,  Tao Wu

IPC: H04B1/10 ,  H03F1/32 ,  H04B1/00

CPC classification number: H04B1/10 ,  H03F1/32 ,  H03F3/45475 ,  H03F2200/336 ,  H03F2200/411 ,  H03F2203/45212 ,  H03F2203/45528 ,  H03F2203/45591 ,  H03F2203/45594 ,  H03F2203/45616 ,  H03G1/0088 ,  H04B1/0017

Abstract: A device includes circuitry configured to receive a signal burst, apply one or more filters to the signal burst based to achieve a predetermined image rejection rate, apply at least one harmonic rejection mode to the signal burst, and amplify the signal burst based on a gain partitioning determination.

Abstract translation: 一种设备包括被配置为接收信号脉冲串的电路，基于信号脉冲串施加一个或多个滤波器以实现预定的图像抑制率，对信号脉冲串施加至少一个谐波抑制模式，并且基于增益放大信号脉冲串 划分确定。

公开(公告)号：US20130279624A1

公开(公告)日：2013-10-24

申请号：US13625183

申请日：2012-09-24

Applicant: BROADCOM CORPORATION

Inventor： Silvian Spiridon ,  Johan van der Tang ,  Han Yan ,  Hua-Feng Chen

IPC: H03M1/00 ,  H04B1/04

CPC classification number: H03M1/0845 ,  H03M1/742

Abstract: According to an exemplary implementation, a transmitter includes a decoder circuit receiving a digital input from a digital back-end circuit. The decoder circuit includes a plurality of decoder cells. Each of the plurality of decoder cells is configured to drive a respective current source cell in a current source circuit so as to convert the digital input into an analog output. Each of the plurality of decoder cells has respective decoder logic. Furthermore, the digital input from the digital back-end circuit is respectively received by each of the plurality of decoder cells.

Abstract translation: 根据示例性实现，发射机包括从数字后端电路接收数字输入的解码器电路。 解码器电路包括多个解码器单元。 多个解码器单元中的每一个被配置为驱动电流源电路中的相应电流源单元，以便将数字输入转换为模拟输出。 多个解码器单元中的每一个具有相应的解码器逻辑。 此外，来自数字后端电路的数字输入分别由多个解码器单元中的每一个接收。