Automatic interrupt system for a data processor
    2.
    发明授权
    Automatic interrupt system for a data processor 失效
    用于数据处理器的自动中断系统

    公开(公告)号:US3286239A

    公开(公告)日:1966-11-15

    申请号:US24122562

    申请日:1962-11-30

    Applicant: BURROUGHS CORP

    CPC classification number: G06F9/4812 G06F11/1438

    Abstract: 1,063,141. Digital electric computers. BURROUGHS CORPORATION. Nov. 1, 1963 [Nov. 30, 1962], No. 43258/63. Headings G4A. The execution by a computer of its normal programme is interrupted (after completion of the current programme step) by a signal on any one of a number of interrupt lines, on which the computer starts to operate in a " control mode " appropriate to the nature of the interruption. A priority order is assigned to the possible interrupting signals so that interruptions requiring rapid action (e.g. main power failure, or certain real-time calculation signals) may be acted upon first. A masking number may be written by programme into a register where it controls which of the theoretically possible interruptions are authorized. Block diagrams (not shown) illustrate the circuitry required, and the steps called for by the control mode circuitry in the various types of interruption (e.g. data transfer to peripheral units) are illustrated by flow sheets.

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