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公开(公告)号：US07415693B1
公开(公告)日：2008-08-19
申请号：US10851355
申请日：2004-05-21
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.
摘要翻译： 一种用于设计系统的方法包括用第一子网的综合结果来缓存第一子网的表示。 响应于确定第二子网的表示与第一子网的表示相同，第一子网的综合结果被用于第二子网。
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公开(公告)号：US07634705B1
公开(公告)日：2009-12-15
申请号：US11403342
申请日：2006-04-12
IPC分类号： H03M13/00
CPC分类号： H03M13/6575 , H03M13/091
摘要： Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.
摘要翻译： 提供了用于在可编程芯片上更有效地实现错误校验码电路的方法和装置。 在一个示例中，循环冗余校验（CRC）异或（XOR）电路被分解以允许在设备上的各种尺寸的查找表（LUT）上的有效实现。 XOR取消因子分解用于将宽的CRC XOR分解成适合各种LUT的块，同时保持对最小化逻辑深度和逻辑区域的关注。 模拟退火用于进一步降低逻辑面积成本。
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公开(公告)号：US08429491B1
公开(公告)日：2013-04-23
申请号：US12623122
申请日：2009-11-20
IPC分类号： H03M13/00
CPC分类号： H03M13/6575 , H03M13/091
摘要： Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.
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4.发明授权Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement 有权用于分割编译时间的合成网表和结果改进质量的方法和装置公开(公告)号：US09230047B1
公开(公告)日：2016-01-05
申请号：US12802669
申请日：2010-06-11
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/504 , G06F17/5045 , G06F17/5072 , G06F17/5077 , G06F2217/78
摘要： A method for designing a system on a target device is disclosed. A partition in the system with a plurality of instances from an extraction netlist is identified. Synthesis optimizations are performed on the partition to generate a synthesis optimization solution. The synthesis optimization solution is applied to the plurality of instances in the system.
摘要翻译： 公开了一种在目标设备上设计系统的方法。 识别具有来自提取网表的多个实例的系统中的分区。 在分区上执行合成优化，以生成合成优化解决方案。 综合优化方案应用于系统中的多个实例。
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5.发明授权Method and apparatus for performing parallel synthesis on a field programmable gate array 有权用于在现场可编程门阵列上执行并行合成的方法和装置公开(公告)号：US08661380B1
公开(公告)日：2014-02-25
申请号：US12070478
申请日：2008-02-19
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method for designing a system to be implemented on a target device includes performing a first synthesis run on an entire design of a system with a first setting to generate a first cell netlist for the entire design of the system. A second synthesis run is performed on the entire design for the system with a second setting and is performed in parallel with the first synthesis procedure to generate a second cell netlist for the entire design of the system. A merged cell netlist is generated that includes a first section of logic from the first netlist and a second section of logic from the second cell netlist.
摘要翻译： 用于设计要在目标设备上实现的系统的方法包括在具有第一设置的系统的整个设计上执行第一合成运行，以生成用于系统的整个设计的第一单元网络列表。 在具有第二设置的系统的整个设计上执行第二合成运行，并且与第一合成过程并行地执行以产生用于系统的整个设计的第二单元网表。 生成包括来自第一网表的逻辑的第一部分和来自第二小区网表的逻辑的第二部分的合并的小区网表。
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公开(公告)号：US07441212B1
公开(公告)日：2008-10-21
申请号：US11222090
申请日：2005-09-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： State machines are identified from a netlist of circuit elements of a user design. Strongly connected components in the netlist are identified as candidates for analysis. The registers of each strongly connected component are identified. An optimal set of inputs and potential state transition logic is identified for the registers in the component. A set of reachable states from an initial state of the registers of a component is determined by simulating state transitions in response to permutations of input values. State machine information is created to assist compilation software in optimizing the user design. Optimizations can include identifying redundant circuit elements based on the set of reachable states and reencoding the state machine with a different state encoding scheme to reduce the amount of state transition and output logic. A subset of the set of reachable states representing a one-hot encoded state machine may be further isolated and optimized.
摘要翻译： 状态机由用户设计的电路元件的网表识别。 网表中的强大连接组件被确定为分析候选者。 识别每个强连接组件的寄存器。 为组件中的寄存器识别最佳的输入和潜在状态转换逻辑。 通过响应于输入值的排列来模拟状态转换来确定来自组件的寄存器的初始状态的一组可达状态。 创建状态机信息以帮助编译软件优化用户设计。 优化可以包括基于可达状态的集合识别冗余电路元件，并且用不同的状态编码方案重新编码状态机以减少状态转换和输出逻辑的量。 可以进一步隔离和优化代表单热编码状态机的一组可达状态的子集。
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公开(公告)号：US07224183B2
公开(公告)日：2007-05-29
申请号：US11201565
申请日：2005-08-10
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： A configuration for a programmable device is determined to implement an incomplete function using at least two logic cells. Function inputs are partitioned into portions associated with first and second logic cells. The partitioning is screened to determine if it is potentially acceptable by determining if a portion of the function can be implemented using a complete look-up table. If the partitioning of the function inputs is potentially acceptable, the function inputs are assigned to the input ports of the logic cells. Variables are assigned to look-up table locations and a correspondence is determined between function input and output values, the variables, and the look-up table locations. Boolean tautology rules are applied to the correspondence to simplify the variables. If the simplified variables are consistent, a configuration is output that includes assignments of function inputs to input ports and look-up table data based on the simplified variables.
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公开(公告)号：US07386828B1
公开(公告)日：2008-06-10
申请号：US11361808
申请日：2006-02-23
CPC分类号： G06F17/5027
摘要： Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.
摘要翻译： 通过创建可编程逻辑块的硬件配置的近似来快速地筛选不太可能提供有效结果的配置来有效地确定具有可编程逻辑块的功能的有效实现。 如果配置通过此第一阶段，则会对该近似进行细化，以便通过硬件配置搜索有效的功能实现。 近似和细化可以使用功能输入变量对逻辑块的划分来减少搜索空间。 可以使用额外的冲突条款来进一步减少搜索空间。 可以分析样本函数或其他以前考虑的函数的实现，以识别可重用于分析其他函数的冲突条款。 功能的潜在实现的表示可以细分为子集并分开分析。 来自每个子集的解的交集是函数的有效实现。
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9.发明授权Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 有权可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器公开(公告)号：US07890910B1
公开(公告)日：2011-02-15
申请号：US11499451
申请日：2006-08-04
IPC分类号： G06F17/50
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译： 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。
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10.发明授权Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 失效可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器公开(公告)号：US07705628B1
公开(公告)日：2010-04-27
申请号：US11486164
申请日：2006-07-12
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/094 , H01L25/00
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译： 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。
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