公开(公告)号：US5045483A

公开(公告)日：1991-09-03

申请号：US503340

申请日：1990-04-02

申请人： Bancherd DeLong ,  Christopher S. Blair ,  George E. Ganschow ,  Thomas S. Crabb

发明人： Bancherd DeLong ,  Christopher S. Blair ,  George E. Ganschow ,  Thomas S. Crabb

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/331

CPC分类号： H01L28/20 ,  H01L21/28525 ,  H01L29/66272 ,  H01L29/6628 ,  Y10S148/123

摘要： A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant drive-in so that fewer total steps are required. The process is compatible with MOS technology so that the bipolar transistor and resistor can be formed on a substrate along with MOS devices.

公开(公告)号：US5139961A

公开(公告)日：1992-08-18

申请号：US503498

申请日：1990-04-02

申请人： Alan G. Solheim ,  Bamdad Bastani ,  James L. Bouknight ,  George E. Ganschow ,  Bancherd Delong ,  Rajeeva Lahri ,  Steve M. Leibiger ,  Christopher S. Blair ,  Rick C. Jerome ,  Madan Biswal ,  Tad Davies ,  Vida Ilderem ,  Ali A. Iranmanesh

发明人： Alan G. Solheim ,  Bamdad Bastani ,  James L. Bouknight ,  George E. Ganschow ,  Bancherd Delong ,  Rajeeva Lahri ,  Steve M. Leibiger ,  Christopher S. Blair ,  Rick C. Jerome ,  Madan Biswal ,  Tad Davies ,  Vida Ilderem ,  Ali A. Iranmanesh

IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/32 ,  H01L21/331 ,  H01L21/762 ,  H01L29/732

CPC分类号： H01L29/6628 ,  H01L21/28525 ,  H01L21/32 ,  H01L21/76205 ,  H01L29/732 ,  Y10S148/01

摘要： A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

公开(公告)号：US5482874A

公开(公告)日：1996-01-09

申请号：US154891

申请日：1993-11-19

申请人： George E. Ganschow

发明人： George E. Ganschow

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L29/10 ,  H01L29/732 ,  H01L21/265 ,  H01R21/22

CPC分类号： H01L21/76208 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/732

摘要： A method for improving the performance of a walled emitter bipolar-junction transistor and the improved walled emitter bipolar junction transistor resulting therefrom are disclosed. The method involves the incorporation of a p-type dopant, preferably boron, at the intersection of the isolation oxide and the emitter-base region. The selective implantation does not affect the transistor's function in any significant way, does not complicate the fabrication process to any significant degree and eliminates known problems of intrinsic base boron segregation and oxide charges in known walled emitter bipolar junction transistors.

摘要翻译： 公开了一种用于提高壁式发射极双极结型晶体管和由此产生的改进的壁式发射极双极结型晶体管的性能的方法。 该方法包括在隔离氧化物和发射极 - 基极区域的交叉处并入p型掺杂剂，优选硼。 选择性注入不会以任何显着的方式影响晶体管的功能，并不会使制造工艺复杂化到任何显着程度，并且消除了已知的壁式发射极双极结型晶体管中本征碱性硼偏析和氧化物电荷的已知问题。

公开(公告)号：US5436496A

公开(公告)日：1995-07-25

申请号：US195901

申请日：1994-02-14

申请人： Rick C. Jerome ,  Ronald P. Kovacs ,  George E. Ganschow ,  Lawrence K. C. Lam ,  James L. Bouknight ,  Frank Marazita ,  Brian McFarlane ,  Ali Iranmanesh

发明人： Rick C. Jerome ,  Ronald P. Kovacs ,  George E. Ganschow ,  Lawrence K. C. Lam ,  James L. Bouknight ,  Frank Marazita ,  Brian McFarlane ,  Ali Iranmanesh

IPC分类号： H01L23/525 ,  H01L27/102 ,  H01L29/47 ,  H01L29/72

CPC分类号： H01L27/1026 ,  H01L23/5256 ,  H01L2924/0002

摘要： A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0.2 microns from the upper surface and has a dopant concentration of about 8.times.1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0.46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium. Mass transport of aluminum atoms through the polysilicon allows aluminum to collect at an interface between the polysilicon and an underlying single crystal silicon layer. Aluminum atoms are supplied from a contact metal. A barrier metal between the contact metal and an underlying polysilicon contact to the emitter is not present. Inhibiting or replacing a TiSi.sub.2 layer over the fuse emitter contact provides better reproducible fusing action. PtSi replaces TiSi.sub.2 if formed over the fuse emitter contact. Separate fuse base implants for the vertical fuse change BJT parameters for improved fusing characteristics. In still another preferred embodiment, codiffusing N type and P type dopants from the polysilicon emitter contact drops a separate fuse mask. The P type codiffused dopants diffuse ahead of the N type emitter dopants into the single crystal to change the base parameters to provide a decreased gain.

摘要翻译： 包括轻掺杂浅发射极30的垂直熔丝结构提供了改进的熔化特性。 该结构包括掩埋的集电极14，覆盖的基底30和在基底30上方的发射体44.在一个优选实施例中，发射器44从上表面延伸约0.2微米，并且每个砷的掺杂剂浓度约为8×1019原子 表面处立方厘米。 轻掺杂的基极区域30在发射极44下方延伸到集电极14的下方约0.46微米。发射极44的上表面包括金属接触点60.使用电流或电压将金属60 /发射极44的界面加热到其共晶熔点 脉冲导致铝通过发射器44短路到基极30.短路发射器编程熔丝。 第二优选实施例使用多晶硅作为互连介质。 通过多晶硅的铝原子的质量传输允许铝在多晶硅和下面的单晶硅层之间的界面处收集。 铝原子由接触金属供应。 接触金属和与发射极的底层多晶硅接触之间的阻挡金属不存在。 在熔丝发射器触点上抑制或更换TiSi2层可提供更好的可再现的熔合动作。 如果形成在熔丝发射体接触点上，则PtSi替代TiSi2。 独立的保险丝底座植入件用于垂直熔断器改变BJT参数，以提高熔断特性。 在又一个优选实施例中，从多晶硅发射器接触端转换N型和P型掺杂剂滴入单独的熔丝掩模。 P型掺杂的掺杂剂在N型发射极掺杂剂之前扩散到单晶中以改变基极参数以提供降低的增益。

公开(公告)号：US5289024A

公开(公告)日：1994-02-22

申请号：US44560

申请日：1993-04-07

申请人： George E. Ganschow

发明人： George E. Ganschow

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L29/10 ,  H01L29/732 ,  H01L29/72 ,  H01L27/12 ,  H01L29/167

CPC分类号： H01L21/76208 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/732

摘要： A bipolar transistor having a base intrinsic region, collector region, and emitter region. The emitter region, collector region, and base intrinsic region each having at least a portion thereof adjacent to an oxide isolation region. The base intrinsic region having a diffusion compensation region therein abutting the oxide isolation region. The diffusion compensation region compensates for the intrinsic concentrations segregating during oxidation, and also compensates for oxide charge contribution to the base region. The additional dopant in the compensation region results in only a small increase in the desired BJT performance and adds minimal complexity in manufacturing. The invention results in the controlled placement of dopants near the "birds's beak" between the emitter and base providing I.sub.CEO leakage current reduction at the emitter edge without affecting the bulk of the active intrinsic base.

摘要翻译： 具有基本本征区域，集电极区域和发射极区域的双极晶体管。 发射极区域，集电极区域和基本本征区域各自具有与氧化物隔离区域相邻的至少一部分。 其中具有扩散补偿区域的基本本征区域邻接氧化物隔离区域。 扩散补偿区补偿在氧化期间分离的固有浓度，并补偿氧化物电荷对基极区的贡献。 补偿区域中的附加掺杂剂仅导致期望的BJT性能的小幅增加，并增加制造中的最小复杂性。 本发明导致在发射极和基极之间的“鸟的喙”附近的掺杂剂的受控放置，从而在发射极边缘处提供ICEO泄漏电流降低而不影响活性本征基体的体积。

公开(公告)号：US5212102A

公开(公告)日：1993-05-18

申请号：US894403

申请日：1992-06-05

申请人： Ali A. Iranmanesh ,  George E. Ganschow

发明人： Ali A. Iranmanesh ,  George E. Ganschow

IPC分类号： H01L27/07 ,  H01L27/102

CPC分类号： H01L27/0766 ,  H01L27/1026

摘要： An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The improved Schottky transistor has a silicide rectifying contact between the base and collector of the transistor, the vertical fuse is provided with a direct contact between an aluminum contact metal and a polysilicon emitter contact.

摘要翻译： 公开了一种用于制造具有相同半导体结构的多晶硅肖特基钳位晶体管和垂直熔断器件的改进方法。 所得结构产生改进的肖特基钳位晶体管和垂直熔断器件。 改进的肖特基晶体管在晶体管的基极和集电极之间具有硅化物整流接触，垂直熔断器在铝接触金属和多晶硅发射极触点之间提供直接接触。

公开(公告)号：US5144404A

公开(公告)日：1992-09-01

申请号：US571346

申请日：1990-08-22

申请人： Ali A. Iranmanesh ,  George E. Ganschow

发明人： Ali A. Iranmanesh ,  George E. Ganschow

IPC分类号： H01L27/07 ,  H01L27/102

CPC分类号： H01L27/0766 ,  H01L27/1026

摘要： An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The improved Schottky transistor has a silicide rectifying contact between the base and collector of the transistor, the vertical fuse is provided with a direct contact between an aluminum contact metal and a polysilicon emitter contact.

摘要翻译： 公开了一种用于制造具有相同半导体结构的多晶硅肖特基钳位晶体管和垂直熔断器件的改进方法。 所得结构产生改进的肖特基钳位晶体管和垂直熔断器件。 改进的肖特基晶体管在晶体管的基极和集电极之间具有硅化物整流接触，垂直熔断器在铝接触金属和多晶硅发射极触点之间提供直接接触。