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    Low contact resistance and low junction leakage metal interconnect contact structure
    1.
    发明授权
    Low contact resistance and low junction leakage metal interconnect contact structure 有权
    低接触电阻和低结漏电金属互连触点结构

    公开(公告)号：US5998873A

    公开(公告)日：1999-12-07

    申请号：US213021

    申请日：1998-12-16

    申请人： Christopher S. Blair ,  Irfan A. Saadat

    发明人： Christopher S. Blair ,  Irfan A. Saadat

    IPC分类号： H01L21/8229 ,  H01L23/485 ,  H01L29/43

    CPC分类号： H01L23/485 ,  H01L2924/0002

    摘要： A low contact resistance and low junction leakage metal interconnect contact structure for use with ICs. The contact structure includes an interconnect dielectric material layer on the surface of an IC semiconductor substrate. The interconnect dielectric material layer has a contact opening which extends to a predetermined region of the semiconductor substrate (e.g. a source region, drain region, or polysilicon gate layer). The contact structure also includes a cobalt (or nickel) silicide interface layer on the surface of the predetermined region that is aligned with the bottom of the contact opening, a cobalt (or nickel) adhesion layer on the sidewall surface of the contact opening, a refractory metal-based barrier layer on the metal adhesion layer and the metal silicide interface layer, and a conductive plug. Manufacturing process steps for such a contact structure include first providing a semiconductor substrate with at least one predetermined region (e.g. a drain region, source region or polysilicon gate layer), followed by depositing an interconnect dielectric material layer on the surface of the semiconductor substrate. Contact openings are formed through the interconnect dielectric material layer to expose the predetermined region. A cobalt (or nickel) adhesion layer is then deposited, followed by the deposition of a refractory metal-based barrier layer, and the reaction of cobalt (or nickel) from the adhesion layer with silicon from the exposed predetermined region to form a metal silicide interface layer. Finally, a conductive plug layer is deposited on the barrier layer, filling the contact opening.

    摘要翻译： 低接触电阻和低结漏电金属互连接触结构用于IC。 接触结构包括在IC半导体衬底的表面上的互连电介质材料层。 互连电介质材料层具有延伸到半导体衬底（例如源极区，漏极区或多晶硅栅极层）的预定区域的接触开口。 接触结构还包括在与接触开口的底部对准的预定区域的表面上的钴（或镍）硅化物界面层，在接触开口的侧壁表面上的钴（或镍）粘附层， 金属粘合层和金属硅化物界面层上的难熔金属基阻挡层和导电塞。 用于这种接触结构的制造工艺步骤包括首先为半导体衬底提供至少一个预定区域（例如漏极区域，源极区域或多晶硅栅极层），然后在半导体衬底的表面上沉积互连电介质材料层。 通过互连电介质材料层形成接触开口以暴露预定区域。 然后沉积钴（或镍）粘合层，然后沉积难熔金属基阻挡层，并且从附着层与钴（或镍）与暴露的预定区域的反应形成金属硅化物 界面层 最后，在阻挡层上沉积导电塞层，填充接触孔。

    Merged single polysilicon bipolar NPN transistor
    2.
    发明授权
    Merged single polysilicon bipolar NPN transistor 失效
    合并单晶双极NPN晶体管

    公开(公告)号：US5925923A

    公开(公告)日：1999-07-20

    申请号：US803122

    申请日：1997-02-20

    申请人： Christopher S. Blair

    发明人： Christopher S. Blair

    IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70

    CPC分类号： H01L29/66272 ,  H01L29/7322

    摘要： A merged single polysilicon bipolar NPN transistor, rather than using separate isolation islands for emitter-base and collector contacts, utilizes a single isolation island. This significantly reduces device area because elimination of the second isolation island used in conventional designs reduces the N+ sink to NPN spacing. Buried layer and isolation layer processing proceed in the conventional manner. At sink mask, however, the mask is sized to uncover one end of the main device active region and a sink implant is performed. At base mask, the sink implant remains covered, rather than being exposed as in the conventional flow. At silicide exclusion, the oxide spacer layer is patterned to exclude silicide from the area above the sink implant region.

    摘要翻译： 合并的单晶多晶硅双极性NPN晶体管，而不是为发射极基极和集电极触点使用单独的隔离岛，利用单个隔离岛。 这显着地减少了器件面积，因为在传统设计中使用的第二隔离岛的消除将N +陷阱减小到NPN间距。 掩埋层和隔离层处理以常规方式进行。 然而，在水槽掩模上，掩模的尺寸被设计成露出主设备有源区域的一端并执行接收器植入。 在底座上，水槽植入物保持覆盖，而不是如常规流中那样暴露。 在硅化物排除时，将氧化物间隔层图案化以从沉积物注入区域上方的区域排除硅化物。

    Integrated monolithic galvanic isolator
    4.
    发明授权
    Integrated monolithic galvanic isolator 有权
    集成单片电流隔离器

    公开(公告)号：US09209091B1

    公开(公告)日：2015-12-08

    申请号：US13198833

    申请日：2011-08-05

    申请人： David Harper ,  Sudarsan Uppili ,  Fanling Hsu Yang ,  David L. Snyder ,  Christopher S. Blair ,  Guillaume Bouche

    发明人： David Harper ,  Sudarsan Uppili ,  Fanling Hsu Yang ,  David L. Snyder ,  Christopher S. Blair ,  Guillaume Bouche

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/1211

    摘要： A semiconductor device is described that includes a first electrical circuit and a second electrical circuit formed on a semiconductor on insulator wafer. The semiconductor on insulator wafer has a layer of semiconducting material formed over a buried layer of insulating material formed over a supporting layer of material. A wide deep trench is formed in the semiconductor on insulator wafer to galvanically isolate the first electrical circuit from the second electrical circuit. The first electrical circuit and the second electrical circuit are coupled together for exchanging energy between the galvanically isolated electrical circuits.

    摘要翻译： 描述了包括形成在绝缘体上半导体晶片上的第一电路和第二电路的半导体器件。 绝缘体上半导体晶片具有形成在绝缘材料的掩埋层上的半导体材料层，其形成在材料的支撑层上。 在半导体绝缘体晶片上形成宽的深沟槽，以将第一电路与第二电路电隔离。 第一电路和第二电路耦合在一起，用于在电隔离的电路之间交换能量。

    Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture
    5.
    发明授权
    Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture 有权

    公开(公告)号：US6103610A

    公开(公告)日：2000-08-15

    申请号：US334132

    申请日：1999-06-15

    申请人： Christopher S. Blair

    发明人： Christopher S. Blair

    IPC分类号： H01L27/085 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/823443

    摘要： A process for the controlled formation of dual thickness cobalt silicide layers on predetermined regions during the manufacturing of an integrated circuit that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, an integrated circuit (IC) structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A cobalt layer is then deposited over the IC structure, followed by the deposition of a titanium capping layer on the cobalt layer. The titanium capping layer is then pattered above predetermined regions of the IC structure. Cobalt in the cobalt layer that is in direct contact with silicon in the exposed silicon surfaces is subsequently reacted to form relatively thick cobalt silicide layers on the predetermined regions and relatively thin cobalt silicide layers elsewhere. The present invention also provides an IC structure with dual thickness cobalt silicide layers. The IC structure includes pluralities of first and second MOS transistor structures having source regions, drain regions and polysilicon gates. Relatively thin cobalt silicide layers are disposed on the first MOS transistor structures with shallow source and drain regions, while relatively thick cobalt silicide layers are disposed on the second MOS transistor structures with deep source and drain regions.

    Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture
    7.
    发明授权
    Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture 有权
    具有双重厚度钴硅酸盐层的集成电路结构及其制造方法

    公开(公告)号：US6040606A

    公开(公告)日：2000-03-21

    申请号：US187306

    申请日：1998-11-04

    申请人： Christopher S. Blair

    发明人： Christopher S. Blair

    IPC分类号： H01L27/085 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/45

    CPC分类号： H01L29/665 ,  H01L21/823443

    摘要： A process for the controlled formation of dual thickness cobalt silicide layers on predetermined regions during the manufacturing of an integrated circuit that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, an integrated circuit (IC) structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A cobalt layer is then deposited over the IC structure, followed by the deposition of a titanium capping layer on the cobalt layer. The titanium capping layer is then pattered above predetermined regions of the IC structure. Cobalt in the cobalt layer that is in direct contact with silicon in the exposed silicon surfaces is subsequently reacted to form relatively thick cobalt silicide layers on the predetermined regions and relatively thin cobalt silicide layers elsewhere. The present invention also provides an IC structure with dual thickness cobalt silicide layers. The IC structure includes pluralities of first and second MOS transistor structures having source regions, drain regions and polysilicon gates. Relatively thin cobalt silicide layers are disposed on the first MOS transistor structures with shallow source and drain regions, while relatively thick cobalt silicide layers are disposed on the second MOS transistor structures with deep source and drain regions.

    摘要翻译： 在制造集成电路期间在预定区域上控制形成双重厚度钴硅化物层的方法，其需要最小数量的步骤并且与标准MOS处理技术兼容。 在根据本发明的方法中，首先提供集成电路（IC）结构。 IC结构包括具有暴露的硅表面的多个MOS晶体管结构，例如源极区，漏极区和多晶硅栅极。 然后在IC结构上沉积钴层，随后在钴层上沉积钛覆盖层。 然后将钛封盖层图案化在IC结构的预定区域上方。 随后在暴露的硅表面中与硅直接接触的钴层中的钴反应以在预定区域上形成相对厚的钴硅化物层，并在其他地方形成相对薄的钴硅化物层。 本发明还提供了具有双重厚度的钴硅化物层的IC结构。 IC结构包括具有源极区，漏极区和多晶硅栅极的多个第一和第二MOS晶体管结构。 在具有浅的源极和漏极区域的第一MOS晶体管结构上设置相对薄的硅化钴层，而在具有深的源极和漏极区域的第二MOS晶体管结构上设置较厚的钴硅化物层。

    Self aligned poly emitter bipolar technology using damascene technique
    8.
    发明授权
    Self aligned poly emitter bipolar technology using damascene technique 失效
    采用镶嵌技术的自对准多晶硅发射极双极技术

    公开(公告)号：US5904536A

    公开(公告)日：1999-05-18

    申请号：US71241

    申请日：1998-05-01

    申请人： Christopher S. Blair

    发明人： Christopher S. Blair

    IPC分类号： H01L21/331 ,  H01L29/737

    CPC分类号： H01L29/66272 ,  H01L29/7373 ,  Y10S148/01 ,  Y10S148/011

    摘要： A polysilicon emitter of a bipolar device is formed utilizing a self-aligned Damascene technique. An oxide mask is patterned over epitaxial silicon implanted to form the intrinsic base. The oxide mask is then etched to form a window. Polysilicon is uniformly deposited over the oxide mask and into the window. The polysilicon is then polished to remove polysilicon outside of the window. Etching of the oxide mask follows, with good selectivity of oxide over silicon. This selectivity produces a polysilicon emitter atop an intrinsic base, the base flush with the silicon surface rather than recessed because of overetching associated with conventional processes.

    摘要翻译： 利用自对准的镶嵌技术形成双极器件的多晶硅发射极。 在植入外延硅上形成氧化物掩模以形成本征基底。 然后蚀刻氧化物掩模以形成窗口。 多晶硅均匀地沉积在氧化物掩模上并进入窗口。 然后抛光多晶硅以除去窗外的多晶硅。 蚀刻氧化物掩模，氧化物在硅上具有良好的选择性。 该选择性在本征基底顶部产生多晶硅发射体，基底与硅表面齐平，而不是由于与常规工艺相关的过蚀刻而凹陷。

    Method of fabricating a self-aligned double polysilicon NPN transistor with poly etch stop
    9.
    发明授权
    Method of fabricating a self-aligned double polysilicon NPN transistor with poly etch stop 失效
    用多层蚀刻停止制造自对准双重多晶硅NPN晶体管的方法

    公开(公告)号：US5882976A

    公开(公告)日：1999-03-16

    申请号：US942102

    申请日：1997-10-01

    申请人： Christopher S. Blair

    发明人： Christopher S. Blair

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66272

    摘要： A method of forming a double polysilicon NPN transistor using a self-aligned process flow. The method includes use of a sacrificial oxide layer deposited over an epitaxial silicon layer prior to deposition and doping of the polysilicon layer from which the base electrode is formed. The sacrificial oxide layer acts as an etch stop for the plasma etch used to pattern the polysilicon layer. After patterning of the doped polysilicon layer, the sacrificial layer is removed using a wet etch. Etching of the oxide layer is performed in a manner which undercuts the doped polysilicon layer. Polysilicon is then deposited by a CVD process in the undercut region from which the initial polysilicon layer has been removed. The CVD deposited polysilicon fills in the gap between the doped polysilicon layer and the underlying epitaxial silicon layer caused by the oxide etch. The CVD deposited polysilicon is then oxidized. The portion of the CVD deposited polysilicon between the doped polysilicon layer and the single crystal silicon remains unoxidized. The oxidized CVD deposited polysilicon is then etched to form sidewall spacers. A second polysilicon layer is then deposited over the substrate and then implanted with an appropriate N+ type dopant. The transistor structure is then annealed to form junctions for the device.

    摘要翻译： 使用自对准工艺流程形成双重多晶硅NPN晶体管的方法。 该方法包括在沉积和掺杂形成基极的多晶硅层之前使用沉积在外延硅层上的牺牲氧化物层。 牺牲氧化物层用作用于图案化多晶硅层的等离子体蚀刻的蚀刻停止。 在掺杂多晶硅层图案化之后，使用湿蚀刻去除牺牲层。 以蚀刻掺杂多晶硅层的方式进行氧化物层的蚀刻。 然后通过CVD工艺将多晶硅沉积在去除了初始多晶硅层的底切区域中。 CVD沉积的多晶硅填充了由氧化物蚀刻引起的掺杂多晶硅层和下面的外延硅层之间的间隙。 然后将CVD沉积的多晶硅氧化。 在掺杂多晶硅层和单晶硅之间的CVD沉积的多晶硅的部分保持未氧化。 然后氧化的CVD沉积的多晶硅被蚀刻以形成侧壁间隔物。 然后将第二多晶硅层沉积在衬底上，然后用适当的N +型掺杂剂注入。 然后对晶体管结构进行退火以形成器件的结。