公开(公告)号：US20190189692A1

公开(公告)日：2019-06-20

申请号：US16281486

申请日：2019-02-21

申请人： Samsung Electronics Co., Ltd.

发明人： Ji-hyun JEONG ,  Gwan-hyeob KOH ,  Dae-hwan KANG

IPC分类号： H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  H01L27/102

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/1026 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

摘要： A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US20190074071A1

公开(公告)日：2019-03-07

申请号：US15909010

申请日：2018-03-01

申请人： NXP B.V.

发明人： Antonius Martinus Jacobus Daanen

IPC分类号： G11C17/16 ,  G11C17/18 ,  G11C17/14 ,  H01L27/112 ,  H01L27/102

CPC分类号： G11C17/165 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  H01L27/1026 ,  H01L27/11206

摘要： A memory system comprising: a memory cell. The memory cell comprising a poly-fuse-resistor; and a bipolar junction transistor having a collector-emitter channel and a base-terminal. The collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal. The base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor.

公开(公告)号：US20180190718A1

公开(公告)日：2018-07-05

申请号：US15906550

申请日：2018-02-27

申请人： Samsung Electronics Co., Ltd.

发明人： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC分类号： H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L27/102

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/1026 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

摘要： A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US20180061756A1

公开(公告)日：2018-03-01

申请号：US15654526

申请日：2017-07-19

申请人： Infineon Technologies AG

发明人： Kerstin Kaemmer ,  Martin Bartels ,  Henning Feick

IPC分类号： H01L23/525 ,  H01L27/112 ,  H01L27/102 ,  G11C17/16

CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C17/18 ,  H01L27/1026 ,  H01L27/11206

摘要： One time programmable memory cell and memory arrayMemory cells and corresponding memory arrays are provided. The memory cell comprises a fusable element and a bipolar transistor arranged adjacent to the fusable element.

公开(公告)号：US09209171B2

公开(公告)日：2015-12-08

申请号：US13812181

申请日：2011-06-20

申请人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

发明人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/07 ,  H01L27/092 ,  H01L27/11 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  H01L27/102 ,  G11C11/412

CPC分类号： H01L27/1203 ,  G11C11/412 ,  G11C16/0408 ,  H01L21/8249 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0623 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/1025 ,  H01L27/1026 ,  H01L27/11 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/1004 ,  H01L29/1033 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7311 ,  H01L29/788 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage.

摘要翻译： 提供了与MOSFET相比具有与常规MOSFET相同的可集成性的半导体元件，即在室温下S值小于60mV /阶的优异的开关特性。 组合MOSFET和具有隧道结的隧道双极晶体管配置了一个半导体元件，其相对于栅极电压的变化（S值小于60mV /次）显示出漏极电流的突然变化，即使在 低电压。

公开(公告)号：US08766235B2

公开(公告)日：2014-07-01

申请号：US13415288

申请日：2012-03-08

申请人： Federica Ottogalli ,  Luca Laurin

发明人： Federica Ottogalli ,  Luca Laurin

IPC分类号： H01L29/06 ,  H01L27/24

CPC分类号： H01L27/24 ,  H01L27/1026 ,  H01L27/2445 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1233

摘要： Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.

摘要翻译： 一些实施方案包括形成BJT的方法。 在半导体材料内形成第一掺杂区域。 在半导体材料内形成第一和第二沟槽以对基座阵列进行图案化，并且沟槽填充有电绝缘材料。 第一类型掺杂区域的上部被反掺杂以形成在第一类型掺杂区域上具有第二类型掺杂区域的第一堆叠，然后对第一堆叠的上部进行反掺杂以形成具有 在一对第一类型掺杂区域之间的第二类型掺杂区域。 一些实施例包括BJT阵列。 基极注入区位于一对发射极/集电极注入区之间。 电绝缘材料与基底植入区域相邻，并且包含至少约7×1016个原子/ cm3的基极注入区掺杂剂。

公开(公告)号：US08476686B2

公开(公告)日：2013-07-02

申请号：US12169648

申请日：2008-07-09

申请人： Armin Tilke

发明人： Armin Tilke

IPC分类号： H01L27/24

CPC分类号： H01L29/66242 ,  H01L27/1026 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： An embodiment relates to a memory cell comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor.

摘要翻译： 一个实施例涉及一种包含电耦合到异质结双极晶体管的可编程电阻存储元件的存储单元。

公开(公告)号：US20130015508A1

公开(公告)日：2013-01-17

申请号：US13183442

申请日：2011-07-15

申请人： Wen-Yueh Jang

发明人： Wen-Yueh Jang

IPC分类号： H01L29/808 ,  H01L21/337

CPC分类号： H01L45/16 ,  H01L27/1022 ,  H01L27/1026 ,  H01L27/226 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/66272 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.

摘要翻译： 对半导体装置及其制造方法进行说明。 半导体器件包括第一导电类型的阱，第二导电类型的第一掺杂区域，第二导电类型的栅极，第一导电类型的第二掺杂区域和隔离结构。 井设置在基板中。 第一掺杂区域设置在阱中。 第一掺杂区域平行布置并沿着第一方向延伸。 栅极设置在基板上。 门平行布置并沿着不同于第一方向的第二方向延伸。 第一掺杂区域中的一个电连接到一个栅极。 每个第二掺杂区域设置在两个相邻栅极之间的第一掺杂区域中。 每个隔离结构设置在两个相邻的第一掺杂区域之间的衬底中。

公开(公告)号：US07723757B2

公开(公告)日：2010-05-25

申请号：US11774452

申请日：2007-07-06

申请人： Tien Fan Ou ,  Wen-Jer Tsai ,  Hsuan Ling Kao ,  Yi Ying Liao

发明人： Tien Fan Ou ,  Wen-Jer Tsai ,  Hsuan Ling Kao ,  Yi Ying Liao

IPC分类号： H01L29/74

CPC分类号： G11C16/0416 ,  G11C16/10 ,  H01L27/1026 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/7923 ,  H01L29/7926

摘要： A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

摘要翻译： 具有电荷存储结构的垂直非易失性存储单元包括具有三个节点的电荷控制结构。 示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

公开(公告)号：US20080111188A1

公开(公告)日：2008-05-15

申请号：US11964022

申请日：2007-12-25

申请人： Chien-Li Kuo

发明人： Chien-Li Kuo

IPC分类号： H01L27/12

CPC分类号： H01L29/7436 ,  G11C11/39 ,  H01L27/0617 ,  H01L27/1026 ,  H01L27/1027 ,  H01L27/105

摘要： An integrated circuit structure is formed on a substrate. The integrated circuit structure includes a logic area and a memory cell area. The memory cell area includes a charge storage area and a non-charge storage area. A dielectric layer is formed on the substrate in the charge storage area. A thyristor is formed on the dielectric layer. A transistor is formed on the substrate in the non-charge storage area.

摘要翻译： 在基板上形成集成电路结构。 集成电路结构包括逻辑区和存储单元区。 存储单元区域包括电荷存储区域和非充电存储区域。 在电荷存储区域中的基板上形成介电层。 在电介质层上形成晶闸管。 在非电荷存储区域中的基板上形成晶体管。