摘要:
A method for reducing a critical dimension of a photoresist pattern while improving a line spacing between distal end portions of pattern lines wherein the method includes providing a substrate including an overlying resist; exposing the resist to an activating light source; baking the resist in a first baking process followed by developing the resist in a first development process to form a first resist pattern; then baking the first resist pattern in a second baking process followed by developing the first resist pattern in a second development process to form a second resist pattern having reduced dimensions; and, then dry trimming the second resist pattern to form a final resist pattern with reduced dimensions compared to the second resist pattern.
摘要:
A method is provided for the creation of contact holes. The invention provides two masks. The first mask, referred to as the packed mask, comprises the desired contact holes, which are part of the creation of a semiconductor device. To the packed mask are added padding holes in order to increase the hole density of the packed mask. An insulation layer is formed to protect the first layer of material. The second mask, referred to an the unpacking mask, comprises openings at the same locations as the locations of the padding holes of the first mask, the openings provided in the second mask have slightly larger dimensions than the padding holes of the first mask. A first exposure is made using the packed mask, a second exposure of the same surface area is made using the unpacking mask. The unpacking mask is used to selectively cover the padding contact holes, resulting in the final image. Two types of unpacking masks can be used, a first type having unpacking holes that surround the desired hole pattern, a second type having unpacking holes that align with the desired hole pattern.
摘要:
The present invention provides a ring-opened polymer, which is prepared by reacting at least one pericyclic olefin elected from those represented by formulae (I) and (II) through ring-opening metathesis polymerization wherein A and B may be the same or different and are independently selected from the group consisting of halogen, hydrogen, C3-20 cyclic or pericyclic alkyl, C1-20 linear and branched alkyl, C6-20 aryl, C7-20 arylalkyl, C7-20 alkylaryl, silyl, alkylsilyl, germyl, alkylgermyl, alkoxycarbonyl, acyl, and a heterocylic group; or, A and B are linked together to form a C3-20 saturated or unsaturated cyclic hydrocarbon group or a substituted or unsubstituted heterocyclic group; C is selected from the group consisting of oxygen, sulfur, —CH2—, and —SiH2—, wherein each R1 is independently selected from C1-20 alkyl and phenyl; each R is independently selected from hydrogen, halogen, and C1-20 alkyl; and each n is an integer from 1 to 6.
摘要:
A method of making a semiconductor device including forming a first sacrificial layer over a first layer to be etched, the first sacrificial layer having a plurality of openings formed therethrough exposing a portion of the first layer; forming a first photoresist layer over the first sacrificial layer and filling the plurality of openings formed through the first sacrificial layer; forming a plurality of openings in the first photoresist layer, each one of the plurality of openings in the first photoresist layer overlying one of the openings in the first sacrificial layer and wherein each opening in the first sacrificial layer has a smaller cross-sectional area then the cross-sectional area of the overlying opening in the first photoresist layer; and etching the first layer through the openings in the first photoresist layer and the first sacrificial layer, comprising exposing the first layer to an etching material.
摘要:
A method of making a semiconductor device including forming a first sacrificial layer over a first layer to be etched, the first sacrificial layer having a plurality of openings formed therethrough exposing a portion of the first layer; forming a first photoresist layer over the first sacrificial layer and filling the plurality of openings formed through the first sacrificial layer; forming a plurality of openings in the first photoresist layer, each one of the plurality of openings in the first photoresist layer overlying one of the openings in the first sacrificial layer and wherein each opening in the first sacrificial layer has a smaller cross-sectional area then the cross-sectional area of the overlying opening in the first photoresist layer; and etching the first layer through the openings in the first photoresist layer and the first sacrificial layer, comprising exposing the first layer to an etching material
摘要:
A method and system is disclosed for selectively forming a pattern for making openings in a substrate. A first set of openings are formed in a first photoresist layer coated on the substrate using a first mask. A developing bottom antireflective coating (BARC) layer is then formed over the first photoresist with the openings filled therewith. A second photoresist layer is formed over the BARC layer. A second set of openings are formed in the second photoresist layer using a second mask exposing the BARC layer directly underneath. The exposed part of the BARC layer is then removed. Subsequently, one or more openings of the first set in the first photoresist layer, after the exposed part of the BARC layer filled therein is removed, are used for forming the openings in the substrate.
摘要:
A method of fabricating a dual-damascene structure comprising the following steps. A structure having a patterned low-k material layer formed thereover is provided. The patterned low-k material layer having an upper surface and at least one via hole formed therethrough. A plug material layer is formed over the patterned low-k material layer and filling the at least one via hole. The plug material layer being comprised of a material dissolvable in TMAH or deionized water. The plug material layer is developed to form a plug within the respective at least one via hole having a height below the upper surface of the patterned low-k material layer. The plug is baked to crosslink the plug material comprising the plug. A trench masking layer is formed and patterned to form a patterned trench masking layer having at least one trench substantially centered over the respective at least one via hole and exposing a portion of patterned low-k material layer adjacent the at least one via hole. Wherein the crosslinked plug material comprising the plug does not adversely interact with the trench masking layer. The patterned low-k material layer is etched at the exposed portion using the patterned trench masking layer as a mask to form a trench opening substantially centered over the via hole. The etching of the patterned low-k material layer also removing some of the plug to form a partially etched plug. The trench opening and the via hole comprising a dual-damascene opening. The partially etched plug is removed from the via hole. A planarized dual-damascene structure is formed within the dual-damascene opening.
摘要:
The present invention provides a cyclic dione polymer, which is a homopolymer or a copolymer of a cyclic dione monomer selected from those represented by formulae (I) and (II) wherein A and B may be the same or different and are independently selected from the group consisting of halogen, hydrogen, C3-20 cyclic or pericyclic alkyl, C1-20 linear and branched alkyl, C6-20 aryl, C7-20 arylalkyl, C7-20 alkylaryl, silyl, alkylsilyl, germyl, alkylgermyl, alkoxycarbonyl, acyl, and a heterocylic group; or, A and B are linked together to form a C3-20 saturated or unsaturated cyclic hydrocarbon group or a substituted or unsubstituted heterocyclic group; C is selected from the group consisting of oxygen, sulfur, wherein each R1 is independently selected from C1-20 alkyl and phenyl.
摘要:
An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.
摘要:
An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.