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1.发明申请公开(公告)号：US20080143375A1
公开(公告)日：2008-06-19
申请号：US11611200
申请日：2006-12-15
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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公开(公告)号：US07512183B2
公开(公告)日：2009-03-31
申请号：US11086718
申请日：2005-03-22
IPC分类号： H04B3/00
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译： 驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。 差分放大器的每个级都用电流源偏置。 驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。 第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。 相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。 第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。
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3.发明申请公开(公告)号：US20080175327A1
公开(公告)日：2008-07-24
申请号：US12058689
申请日：2008-03-29
IPC分类号： H04B3/00
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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公开(公告)号：US07239213B2
公开(公告)日：2007-07-03
申请号：US11209549
申请日：2005-08-23
IPC分类号： H01P1/00
CPC分类号： H04L25/0272 , H04B3/32
摘要： Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.
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公开(公告)号：US07835453B2
公开(公告)日：2010-11-16
申请号：US12350120
申请日：2009-01-07
IPC分类号： H04B3/00
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译： 驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。 差分放大器的每个级都用电流源偏置。 驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。 第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。 相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。 第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。
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公开(公告)号：US20090113107A1
公开(公告)日：2009-04-30
申请号：US12350120
申请日：2009-01-07
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译： 驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。 差分放大器的每个级都用电流源偏置。 驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。 第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。 相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。 第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。
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7.发明授权公开(公告)号：US07477068B2
公开(公告)日：2009-01-13
申请号：US12058689
申请日：2008-03-29
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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8.发明授权公开(公告)号：US07382151B1
公开(公告)日：2008-06-03
申请号：US11611200
申请日：2006-12-15
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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公开(公告)号：US07242339B1
公开(公告)日：2007-07-10
申请号：US11333613
申请日：2006-01-17
申请人： Bao G. Truong , Joel D. Ziegelbein
发明人： Bao G. Truong , Joel D. Ziegelbein
IPC分类号： H03M1/78
CPC分类号： H03K17/6872 , H03K17/6874
摘要： A reference generator circuit has a resistor string between the potentials of the power supply voltage that is partitioned into a top string, a middle string, and a bottom string. PFET devices are used to couple the positive power supply voltage a selected node of the top string in response to first control signals and complementary second control signals are used to control NFET devices that couple the ground power supply voltage to a selected node of the bottom string. If a resistor is effectively removed from the top string a corresponding resistor is effectively added in the bottom string keeping the total resistance in the resistor string substantially constant. A pass gate network is used to select between nodes of the middle string as a vernier for generating small step sizes.
摘要翻译： 参考发生器电路在电源电压的电位之间具有分隔成顶部串，中间串和底部串的电阻串。 PFET装置用于响应于第一控制信号将正电源电压耦合到顶部串的所选节点，并且互补的第二控制信号用于控制将接地电源电压耦合到底部串的选定节点的NFET装置 。 如果从顶部串中有效地去除电阻器，则在底部串中有效地添加相应的电阻器，从而保持电阻串中的总电阻基本上恒定。 传递门网络用于在中间串的节点之间选择用于生成小步长的游标。
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10.发明授权Cache array power savings through a design structure for valid bit detection 失效通过用于有效位检测的设计结构来缓存阵列功耗公开(公告)号：US08014215B2
公开(公告)日：2011-09-06
申请号：US12635234
申请日：2009-12-10
申请人： Michael J. Lee , Bao G. Truong , Samuel I. Ward
发明人： Michael J. Lee , Bao G. Truong , Samuel I. Ward
IPC分类号： G11C7/00
CPC分类号： G06F12/0895 , G06F2212/1028 , G11C11/412 , Y02D10/13
摘要： A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.
摘要翻译： 提供了一种机制，用于选通已被无效的高速缓存访问存储器中的任何行的读取访问。 高速缓存存取存储器中的地址解码器发送存储器访问到非门控字线驱动器和与存储器访问相关联的选通字线驱动器。 响应于非门控字线驱动器将存储器访问确定为读取访问，非门控字线驱动器将存储在有效位存储器单元中的数据输出到门控字线驱动器。 门控字线驱动器确定来自非门控字线驱动器的来自有效位存储器单元的数据是否响应于门控字线驱动器确定存储器访问作为读取访问而指示有效数据或无效数据，并且拒绝数据的输出 在与该门控字幕驱动器相关联的一行存储器单元响应于该数据无效。
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