公开(公告)号：US20050226234A1

公开(公告)日：2005-10-13

申请号：US11146449

申请日：2005-06-07

申请人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US20070214230A1

公开(公告)日：2007-09-13

申请号：US11717511

申请日：2007-03-13

申请人： Barton Sano ,  Joseph Rowlands ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  Laurent Moll ,  Manu Gulati

IPC分类号： G06F15/167

CPC分类号： G06F13/4022

摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

公开(公告)号：US20070291781A1

公开(公告)日：2007-12-20

申请号：US11803637

申请日：2007-05-15

申请人： Barton Sano ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Laurent Moll ,  Manu Gulati

IPC分类号： H04L12/56

CPC分类号： H04L47/40

摘要： An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

公开(公告)号：US08208470B2

公开(公告)日：2012-06-26

申请号：US12573754

申请日：2009-10-05

申请人： Manu Gulati ,  Laurent Moll ,  Barton Sano

发明人： Manu Gulati ,  Laurent Moll ,  Barton Sano

IPC分类号： H04L12/28

CPC分类号： H04L12/56

摘要： A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication. The multiple processor device then generates the associated data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet.

摘要翻译： 多处理器设备部分地根据基于连接的点对点链路的控制分组格式生成用于至少一个基于无连接的分组的控制分组，并且部分地不符合控制分组格式。 例如，多处理器设备生成控制分组，以在不遵守控制分组格式的情况下包括以下指示：至少一个基于无连接的分组正被传输的指示，多个 与至少一个基于无连接的分组关联的虚拟频道，包括在相关数据分组中的数据量的指示，至少一个基于无连接的分组的状态以及错误状态指示。 然后，多处理器设备根据基于连接的点对点链路的数据分组格式生成相关联的数据分组，其中数据分组包括至少一个基于无连接的分组的至少一部分。

公开(公告)号：US20100020816A1

公开(公告)日：2010-01-28

申请号：US12573754

申请日：2009-10-05

申请人： Manu Gulati ,  Laurent Moll ,  Barton Sano

发明人： Manu Gulati ,  Laurent Moll ,  Barton Sano

IPC分类号： H04L12/56 ,  H04L29/06

CPC分类号： H04L12/56

摘要： A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication. The multiple processor device then generates the associated data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet.

摘要翻译： 多处理器设备部分地根据基于连接的点对点链路的控制分组格式生成用于至少一个基于无连接的分组的控制分组，并且部分地不符合控制分组格式。 例如，多处理器设备生成控制分组，以在不遵守控制分组格式的情况下包括以下指示：至少一个基于无连接的分组正被传输的指示，多个 与至少一个基于无连接的分组关联的虚拟频道，包括在相关数据分组中的数据量的指示，至少一个基于无连接的分组的状态以及错误状态指示。 然后，多处理器设备根据基于连接的点对点链路的数据分组格式生成相关联的数据分组，其中数据分组包括至少一个基于无连接的分组的至少一部分。

公开(公告)号：US07609718B2

公开(公告)日：2009-10-27

申请号：US10356661

申请日：2003-01-31

申请人： Manu Gulati ,  Laurent Moll ,  Barton Sano

发明人： Manu Gulati ,  Laurent Moll ,  Barton Sano

IPC分类号： H04J3/16

CPC分类号： H04L12/56

摘要： A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication. The multiple processor device then generates the associated data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet.

摘要翻译： 多处理器设备部分地根据基于连接的点对点链路的控制分组格式生成用于至少一个基于无连接的分组的控制分组，并且部分地不符合控制分组格式。 例如，多处理器设备生成控制分组，以在不遵守控制分组格式的情况下包括以下指示：至少一个基于无连接的分组正被传输的指示，多个 与至少一个基于无连接的分组关联的虚拟频道，包括在相关数据分组中的数据量的指示，至少一个基于无连接的分组的状态以及错误状态指示。 然后，多处理器设备根据基于连接的点对点链路的数据分组格式生成相关联的数据分组，其中数据分组包括至少一个基于无连接的分组的至少一部分。

公开(公告)号：US07403525B2

公开(公告)日：2008-07-22

申请号：US10356323

申请日：2003-01-31

申请人： Barton Sano ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Laurent Moll ,  Manu Gulati

IPC分类号： H04L12/56

CPC分类号： H04L45/38 ,  H04L49/25

摘要： According to the present invention, the multiple processor device determines routing for a plurality of data segments. In determining the routing, the multiple processor device first receives the plurality of data segments. The plurality of data segments include multiplexed data fragments from at least one of a plurality of virtual channels. Further, a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The multiple processor device then applies at least one routing rule to one of the plurality of data segments to produce at least one result corresponding to the one of the plurality of data segments. The multiple processor device then interprets the at least one result to determine whether sufficient information is available to render a routing decision for the one of the plurality of data segments. When the multiple processor device determines that there is sufficient information to render a routing decision, the multiple processor device determines routing of the one of the plurality of data segments. When there is insufficient information to render a routing decision, the one of the plurality of data segments is stored in a buffer corresponding to a packet in which the one of the plurality of data segments was received. These operations are repeated for subsequent data segments.

摘要翻译： 根据本发明，多处理器设备确定多个数据段的路由。 在确定路由时，多处理器设备首先接收多个数据段。 多个数据段包括来自多个虚拟通道中的至少一个的多路复用数据片段。 此外，多个数据段的数据段对应于多路复用数据段中的一个。 多处理器设备然后将至少一个路由规则应用于多个数据段中的一个，以产生与多个数据段中的一个对应的至少一个结果。 多处理器设备然后解释至少一个结果以确定足够的信息是否可用于为多个数据段中的一个数据段呈现路由决定。 当多处理器设备确定有足够的信息来呈现路由决定时，多处理器设备确定该多个数据段之一的路由。 当没有足够的信息来呈现路由决定时，多个数据段中的一个数据段被存储在与其中接收多个数据段中的一个数据段的分组相对应的缓冲器中。 对后续数据段重复这些操作。

公开(公告)号：US20050147105A1

公开(公告)日：2005-07-07

申请号：US11069313

申请日：2005-03-01

申请人： Barton Sano ,  Koray Oner ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Koray Oner ,  Laurent Moll ,  Manu Gulati

IPC分类号： G06F13/28 ,  H04L12/56

CPC分类号： H04L49/10 ,  H04L49/602

摘要： An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

公开(公告)号：US07680140B2

公开(公告)日：2010-03-16

申请号：US11803637

申请日：2007-05-15

申请人： Barton Sano ,  Laurent R. Moll ,  Manu Gulati

发明人： Barton Sano ,  Laurent R. Moll ,  Manu Gulati

IPC分类号： H04L12/56

CPC分类号： H04L47/40

摘要： An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

摘要翻译： 集成电路包括用于接收分组的接收电路，用于发送分组的发送电路，用于向存储器控制器传送分组的分组DMA电路和用于选择性地将接收电路耦合到发送电路的开关。 集成电路可以灵活地合并和拆分分组流，以提供要应用于分组流内的不同分组的各种分组处理/分组路由功能。 装置可以包括两个或更多个集成电路，其可以在相应的接收和发送电路之间传送分组。

公开(公告)号：US20050078601A1

公开(公告)日：2005-04-14

申请号：US10684871

申请日：2003-10-14

申请人： Laurent Moll ,  Barton Sano ,  Thomas Petersen

发明人： Laurent Moll ,  Barton Sano ,  Thomas Petersen

IPC分类号： H04J1/16 ,  H04L12/56

CPC分类号： H04L45/60 ,  H04L45/00 ,  H04L45/54 ,  H04L45/745 ,  H04L49/109

摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.

摘要翻译： 结合用于计算输入分组的路由信息​​的并行路由方案来描述基本上在单个CMOS集成电路上实现的多处理器交换设备。 使用可编程散列和路由路由方案，哈希和路由电路可以针对各种应用进行编程，例如路由，流分解或负载平衡。