公开(公告)号：US20050226234A1

公开(公告)日：2005-10-13

申请号：US11146449

申请日：2005-06-07

申请人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US20070214230A1

公开(公告)日：2007-09-13

申请号：US11717511

申请日：2007-03-13

申请人： Barton Sano ,  Joseph Rowlands ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  Laurent Moll ,  Manu Gulati

IPC分类号： G06F15/167

CPC分类号： G06F13/4022

摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

公开(公告)号：US20050223188A1

公开(公告)日：2005-10-06

申请号：US11146450

申请日：2005-06-07

申请人： Laurent Moll ,  James Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph Rowlands

发明人： Laurent Moll ,  James Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph Rowlands

IPC分类号： G06F3/00 ,  G06F9/42 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1684

摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

摘要翻译： 节点包括耦合到节点内的互连的至少一个代理和输入/输出（I / O）电路。 I / O电路被配置为在使用期间一个或多个其他节点耦合到的全局互连上进行通信。 在互连上发送的地址在节点的第一本地地址空间中，并且在全局互连上发送的地址在全局地址空间中。 第一本地地址空间至少包括用于寻址节点的至少第一资源的第一区域。 该节点在使用期间是可编程的，以重新定位第一本地地址空间内的第一区域，由此第一本地地址空间中的相同数值和对应于耦合到全局互连的其他节点之一的第二本地地址空间 到使用中的节点的第一个资源。

公开(公告)号：US20050251631A1

公开(公告)日：2005-11-10

申请号：US11182123

申请日：2005-07-15

申请人： Joseph Rowlands ,  Manu Gulati

发明人： Joseph Rowlands ,  Manu Gulati

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0824

摘要： A shared memory system includes a plurality of processing nodes and a packetized input/output link. Each of the plurality of processing nodes includes a processing resource and memory. The packetized I/O link operably couples the plurality of processing nodes together. One of the plurality of processing nodes is operably coupled to: initiate coherent memory transactions such that another one of plurality of processing nodes has access to a home memory section of the memory of the one of the plurality of processing nodes; and facilitate transmission of a coherency transaction packet between the memory of the one of the plurality of processing nodes and the another one of the plurality of processing nodes over the packetized I/O link.

摘要翻译： 共享存储器系统包括多个处理节点和分组化的输入/输出链路。 多个处理节点中的每一个包括处理资源和存储器。 打包的I / O链路将多个处理节点可操作地耦合在一起。 多个处理节点中的一个可操作地耦合到：发起相干存储器事务，使得多个处理节点中的另一个处理节点可以访问多个处理节点之一的存储器的归属存储器部分; 并且便于通过分组化的I / O链路在多个处理节点之一的存储器与多个处理节点中的另一个处理节点之间传输一致性事务分组。

公开(公告)号：US20050081127A1

公开(公告)日：2005-04-14

申请号：US10684953

申请日：2003-10-14

申请人： Joseph Rowlands ,  Laurent Moll

发明人： Joseph Rowlands ,  Laurent Moll

IPC分类号： G06F11/00 ,  G06F11/27

CPC分类号： G06F11/0784 ,  G06F11/0724 ,  G06F11/0745 ,  G06F11/2242

摘要： In accordance with the present invention a system for detecting transaction errors in a system comprising a plurality of data processing devices using a common system interconnect bus, comprises a node controller operably connected to said system interconnect bus and a plurality of interface agents communicatively coupled to said node controller. Error corresponding to transactions between said interface agents and other processing modules in said system are directed to said node controller; and wherein transaction errors that would not normally be communicated to said system interconnect bus are communicated by said node controller to said system interconnect bus to be available for detection. In an embodiment of the present invention, the interface agents operate in accordance with the hypertransport protocol. A system control and debug unit and a trace cache operably connected to the system bus can be used to diagnose and store errors conditions.

摘要翻译： 根据本发明，一种用于检测包括使用公共系统互连总线的多个数据处理设备的系统中的事务错误的系统包括可操作地连接到所述系统互连总线的节点控制器和通信地耦合到所述系统互连总线的多个接口代理 节点控制器。 与所述接口代理和所述系统中的其他处理模块之间的事务相对应的错误被引导到所述节点控制器; 并且其中通常不会传送到所述系统互连总线的事务错误由所述节点控制器传送到所述系统互连总线以供检测。 在本发明的实施例中，接口代理根据超传输协议进行操作。 可操作地连接到系统总线的系统控制和调试单元和跟踪缓存可用于诊断和存储错误状况。

公开(公告)号：US20050080941A1

公开(公告)日：2005-04-14

申请号：US10684909

申请日：2003-10-14

申请人： Laurent Moll ,  Joseph Rowlands

发明人： Laurent Moll ,  Joseph Rowlands

IPC分类号： G06F3/00 ,  H04L12/433

CPC分类号： H04L12/433

摘要： A system for synchronizing configuration information in a plurality of data processing devices using a common system interconnect bus. The present invention provides a method and apparatus for enforcing automatic updates to the configuration registers in various agents in the data processing system. The interface agent are not required to have target/response logic to respond to internal and external configuration accesses. In and embodiment of the present invention, a node controller, which may comprise a configuration block, is operably connected to a system interconnect bus and a switch. A plurality of interface agents are connected to the switch, with each of the interface agents comprising a configuration space register, a configuration space shadow register and a control and status register (CSR). A token ring connected to the node controller is operable to transmit data from the node controller to a plurality of interface agents connected to the token ring, thereby providing a system for updating the various configuration registers in each of the agents. A transaction from an interface agent is transferred to the node controller which transfers the transaction onto the system interconnect bus. The transaction on the system interconnected bus is detected by the configuration block of the node controller and is then transmitted on the token ring to each of the agents connected thereto. The information transmitted on the token ring is used to update the information in the configuration space registers and configuration space shadow registers of each of the agents connected to the token ring. In an embodiment of the invention the interface agents are configured in accordance with the Hypertransport protocol. In this embodiment, the configuration comprises a HT configuration space register and the configuration space shadow register comprise a HT configuration space shadow register.

摘要翻译： 一种用于使用公共系统互连总线在多个数据处理装置中同步配置信息的系统。 本发明提供一种用于在数据处理系统中的各种代理中实施对配置寄存器的自动更新的方法和装置。 接口代理不需要具有响应内部和外部配置访问的目标/响应逻辑。 在本发明的实施例中，可以包括配置块的节点控制器可操作地连接到系统互连总线和开关。 多个接口代理连接到交换机，每个接口代理包括配置空间寄存器，配置空间影子寄存器和控制和状态寄存器（CSR）。 连接到节点控制器的令牌环可操作以将数据从节点控制器发送到连接到令牌环的多个接口代理，从而提供用于更新每个代理中的各种配置寄存器的系统。 来自接口代理的事务被传送到将事务传送到系统互连总线上的节点控制器。 系统互连总线上的事务由节点控制器的配置块检测，然后在令牌环上传送到与其连接的每个代理。 在令牌环上发送的信息用于更新连接到令牌环的每个代理的配置空间寄存器和配置空间影子寄存器中的信息。 在本发明的实施例中，根据Hypertransport协议配置接口代理。 在该实施例中，该配置包括HT配置空间寄存器，并且配置空间影子寄存器包括HT配置空间影子寄存器。

公开(公告)号：US08225315B1

公开(公告)日：2012-07-17

申请号：US11933319

申请日：2007-10-31

申请人： Yu Qing Cheng ,  John Gregory Favor ,  Peter N. Glaskowsky ,  Laurent R. Moll ,  Carlos Puchol ,  Joseph Rowlands ,  Seungyoon Peter Song

发明人： Yu Qing Cheng ,  John Gregory Favor ,  Peter N. Glaskowsky ,  Laurent R. Moll ,  Carlos Puchol ,  Joseph Rowlands ,  Seungyoon Peter Song

IPC分类号： G06F9/455 ,  G06F15/76

CPC分类号： G06F9/455 ,  G06F9/4825 ,  Y02D10/24

摘要： A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.

摘要翻译： 一种包括物理核心和第一虚拟核心的虚拟核心管理系统，包括与执行第一程序相关联的逻辑状态的集合。 第一个虚拟内核映射到物理内核。 虚拟核心管理系统还包括第二虚拟核心，其包括与执行第二程序相关联的逻辑状态的集合，虚拟核心管理组件被配置为从物理核心取消映射第一虚拟核心并将第二虚拟核心映射到 响应虚拟核心管理组件检测物理内核空闲的物理核心。

公开(公告)号：US09130856B2

公开(公告)日：2015-09-08

申请号：US13752226

申请日：2013-01-28

申请人： Sailesh Kumar ,  Eric Norige ,  Joji Philip ,  Mahmud Hassan ,  Sundari Mitra ,  Joseph Rowlands

发明人： Sailesh Kumar ,  Eric Norige ,  Joji Philip ,  Mahmud Hassan ,  Sundari Mitra ,  Joseph Rowlands

IPC分类号： G01R31/08 ,  H04L12/803

CPC分类号： H04L47/125 ,  H04L45/66 ,  H04L47/70

摘要： Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.

摘要翻译： 本文描述的系统和方法涉及基于网络片上（NoC）互连的解决方案，其基于系统业务流的带宽要求，自动且动态地确定NoC互连系统中所需的层数。 通过在映射不同NoC层的信道和路由之间的业务流的负载分担来动态分配和最小化层数。 可以分配附加层以提供可能需要用于死锁避免的附加虚拟通道并且维持各种系统流之间的隔离属性。 可以一起执行用于附加带宽和附加虚拟通道（VC）的层分配。

公开(公告)号：US07814298B1

公开(公告)日：2010-10-12

申请号：US11941883

申请日：2007-11-16

申请人： Richard Thaik ,  John Gregory Favor ,  Joseph Rowlands ,  Leonard Eric Shar ,  Matthew Ashcraft

发明人： Richard Thaik ,  John Gregory Favor ,  Joseph Rowlands ,  Leonard Eric Shar ,  Matthew Ashcraft

IPC分类号： G06F9/30

CPC分类号： G06F12/0875 ,  Y02D10/13

摘要： A method, system and computer program product for promoting a trace in an instruction processing circuit is disclosed. They comprise determining if a current trace is promotable and determining if a next trace is appendable to the current trace. They include promoting the current trace and the next trace if the current trace is promotable and the next trace is appendable.

摘要翻译： 公开了一种用于促进指令处理电路中的迹线的方法，系统和计算机程序产品。 它们包括确定当前跟踪是否可提升，并确定下一个跟踪是否可附加到当前跟踪。 它们包括在当前跟踪是可升级的并且下一个跟踪是可附加的情况下促进当前跟踪和下一个跟踪。

公开(公告)号：US07797563B1

公开(公告)日：2010-09-14

申请号：US11450103

申请日：2006-06-09

申请人： Laurent R. Moll ,  Joseph Rowlands

发明人： Laurent R. Moll ,  Joseph Rowlands

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

摘要： A system includes a plurality of processors and a monitor coupled to each of the plurality of processors. The monitor is located in a location separate from the plurality of processors. At least some portions of one or more of the plurality of processors enter a power-conservation mode after the one or more of the plurality of processors request one or more resources. The system further includes a power-management controller. The power-management controller is operative to cause the at least some portions of the one or more of the plurality of processors to enter the power-conservation mode after the one or more of the plurality of processors request the one or more resources.

摘要翻译： 系统包括多个处理器和耦合到多个处理器中的每一个的监视器。 显示器位于与多个处理器分离的位置。 所述多个处理器中的一个或多个处理器的至少一些部分在所述多个处理器中的一个或多个处理器请求一个或多个资源之后进入功率保存模式。 该系统还包括一个电源管理控制器。 功率管理控制器可操作以在所述多个处理器中的一个或多个处理器请求所述一个或多个资源之后，使所述多个处理器中的一个或多个处理器的所述至少一些部分进入所述功率保存模式。