公开(公告)号：US4072888A

公开(公告)日：1978-02-07

申请号：US572593

申请日：1975-04-28

申请人： Bastian Bechtle ,  Claus Schuenemann ,  Gisbert Skudelny ,  Wilhelm Spruth ,  Helmut Weis ,  Volker Zimmermann

发明人： Bastian Bechtle ,  Claus Schuenemann ,  Gisbert Skudelny ,  Wilhelm Spruth ,  Helmut Weis ,  Volker Zimmermann

IPC分类号： H02P8/00 ,  H02P8/14 ,  G05B19/40

CPC分类号： H02P8/14

摘要： Method and apparatus for controlling a stepping motor by storing in a memory, delay time values for the application of motor advance pulses and using motor feedback pulses to access the memory and read out corresponding time delay values after each of which a motor advance pulse is to be generated. The stored time delay values are optimized as to phase angle for the motor advance pulses for acceleration, constant run and deceleration modes of the motor after consideration of motor characteristics and load. Not all feedback pulses have a corresponding time delay value and certain feedback pulses may have two or more time delay values stored therefor. Also disclosed are improved motor coil switching circuits.

摘要翻译： 用于通过存储在存储器中来控制步进电动机的方法和装置，用于施加电动机提前脉冲的延迟时间值，并且使用电动机反馈脉冲来访问存储器，并且在每个电动机提前脉冲之后读出相应的时间延迟值 生成。 考虑到电机特性和负载后，对电机的加速度，恒定运行和减速模式的电机提前脉冲的相位角进行优化。 不是所有的反馈脉冲具有对应的时间延迟值，并且某些反馈脉冲可以具有存储的两个或更多个时间延迟值。 还公开了改进的电动机线圈切换电路。

公开(公告)号：US4400793A

公开(公告)日：1983-08-23

申请号：US350456

申请日：1982-02-19

申请人： Claus Schuenemann

发明人： Claus Schuenemann

IPC分类号： G11C11/56 ,  G06F12/0802 ,  G11C19/00 ,  G11C19/28 ,  G11C27/04 ,  G06F13/06

CPC分类号： G06F12/0802 ,  G11C19/287

摘要： To reduce the mean access time to storage blocks in CCD storage, a block which is most likely to be accessed next is detected after each access. While the accessed block is being processed, a selected block is moved at the high cyclic speed of the CCD storage to a shift position, and the CCD storage is then switched to the low speed. The distance of the shift position from a read/write position is such that it can be covered by the selected block at low speed within the mean time between two accesses to the CCD storage. At the time of the next access, the selected block is very likely to be close to the read/write position. In systems with virtual addressing, the block with the next virtual address would be the selected block. In other layouts, the access sequences to the CCD blocks are stored and are subsequently used to select the block which is most likely to be accessed next.

摘要翻译： 为了减少CCD存储器中存储块的平均访问时间，在每次访问之后检测到最可能被访问的块。 当访问的块正在被处理时，所选择的块以CCD存储器的高循环速度移动到移位位置，然后将CCD存储器切换到低速。 移位位置与读/写位置的距离使得它可以在对CCD存储器的两次访问之间的平均时间内以低速被所选块覆盖。 在下一次访问时，所选择的块很可能接近读/写位置。 在具有虚拟寻址的系统中，具有下一个虚拟地址的块将是所选的块。 在其他布局中，存储对CCD块的访问序列，并随后用于选择最有可能被访问的块。

公开(公告)号：US4023147A

公开(公告)日：1977-05-10

申请号：US620481

申请日：1975-10-06

申请人： Claus Schuenemann ,  Frank Tsui

发明人： Claus Schuenemann ,  Frank Tsui

IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C15/04 ,  G11C11/02

CPC分类号： G11C11/404 ,  G11C15/043

摘要： For associative operation of a storage circuit, two field-effect transistors form one storage cell, i. e. that together with associated capacitors they store either a 1 or a 0. A word line is connected to one electrode of each field-effect transistor in a storage row. At one end of the word line a sensing amplifier with latch characteristics is arranged so that the information sensed by this circuit is amplified and subsequently latched or stored. For the associative operation of the circuit arrangement, two query lines Q0 and Q1 are provided for a bit position. When only one field-effect transistor with a series-connected capacitor is used, the bits of one bit position of the various words are simultaneously written, and the bit positions are addressed one after the other. For a bit position which is queried by means of a key or an identifier word bit "1" the true value of the bit is applied. For a bit position which is queried by means of a key or an identifier word bit "0" the complement of the bit is applied. Querying is effected in that lines Q of all bit positions to be queried are set to V.sub.n. Only when the key or identifier word and the queried bits concur with each other in full does no signal occur on the word line.

摘要翻译： 对于存储电路的相关操作，两个场效应晶体管形成一个存储单元， e。 与相关联的电容器一起存储1或0.一条字线连接到存储行中每个场效应晶体管的一个电极。 在字线的一端，布置具有锁存特性的感测放大器，使得由该电路感测的信息被放大并随后被锁存或存储。 对于电路装置的关联操作，为位位置提供两条查询线Q0和Q1。 当仅使用一个具有串联电容器的场效应晶体管时，各个字的一位位置的位被同时写入，并且一个接一个地寻址位位置。 对于通过键或标识符字位“1”查询的位位置，应用该位的真值。 对于通过键或标识符字位“0”查询的位位置，应用该位的补码。 查询是由待查询的所有位位置的行Q设定为Vn。 只有当密钥或标识符字和查询位相互完全相符时，字线上不会出现任何信号。