公开(公告)号：US07580278B2

公开(公告)日：2009-08-25

申请号：US11868992

申请日：2007-10-09

申请人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

发明人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

摘要： A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver. The set program control circuit controls the duration of the step-down set current in accordance with at least one of data contained in an mode register set (MRS) and a conductive state of a fuse element.

摘要翻译： 可变电阻存储器件包括具有多个存储器单元的存储单元阵列，一个写入驱动器，其将降压设定电流提供给存储器单元，其中降压设定电流包括多个连续的步骤，其降低电流幅度 以及控制由写入驱动器提供的降压设定电流的持续时间的设定程序控制电路。 设定程序控制电路根据包含在模式寄存器组（MRS）和熔丝元件的导通状态中的至少一个数据来控制降压设定电流的持续时间。

公开(公告)号：US20070133267A1

公开(公告)日：2007-06-14

申请号：US11319284

申请日：2005-12-29

申请人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

发明人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

摘要： A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

摘要翻译： 相变存储器件包括具有相变材料的存储单元，向该存储单元提供降压设定电流的写入驱动器，其中降压设定电流包括减小电流幅度的多个连续步骤，以及 控制由写入驱动器提供的降压设定电流的持续时间的设定程序控制电路。

公开(公告)号：US07295464B2

公开(公告)日：2007-11-13

申请号：US11319284

申请日：2005-12-29

申请人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

发明人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

摘要： A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

公开(公告)号：US20060120148A1

公开(公告)日：2006-06-08

申请号：US11238381

申请日：2005-09-29

申请人： Sung-Min Kim ,  Eun-Jung Yun ,  Jong-Soo Seo ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Byung-Seo Kim

发明人： Sung-Min Kim ,  Eun-Jung Yun ,  Jong-Soo Seo ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Byung-Seo Kim

IPC分类号： G11C11/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

公开(公告)号：US08259511B2

公开(公告)日：2012-09-04

申请号：US13064672

申请日：2011-04-07

申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

摘要翻译： 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

公开(公告)号：US20110242886A1

公开(公告)日：2011-10-06

申请号：US13091238

申请日：2011-04-21

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/21

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

摘要翻译： 提供了使用相变存储器件的装置和系统。 相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多个复位线中相应的一个。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

公开(公告)号：US08023319B2

公开(公告)日：2011-09-20

申请号：US12457319

申请日：2009-06-08

申请人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

发明人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

IPC分类号： G11C11/00

CPC分类号： G11C29/808 ,  G11C13/0004

摘要： The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

摘要翻译： 所述相变存储器件包括多个存储体，连接到所述多个存储体的多个局部导体线，连接到所述多个局部导体线的至少一个全局导体线，以及至少一个修理控制电路， 选择性地将所述至少一个全局导体线中的至少一个与至少一个冗余全局导体线替换并且被配置为用至少一个冗余局部导体线选择性地替换所述多条局部导体线中的至少一个。

公开(公告)号：US07751232B2

公开(公告)日：2010-07-06

申请号：US11953146

申请日：2007-12-10

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US07391644B2

公开(公告)日：2008-06-24

申请号：US11605212

申请日：2006-11-29

申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

公开(公告)号：US20080137402A1

公开(公告)日：2008-06-12

申请号：US11949342

申请日：2007-12-03

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

摘要翻译： 提供了使用相变存储器件的装置和系统。 相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多个复位线中相应的一个。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。