公开(公告)号：US20060256612A1

公开(公告)日：2006-11-16

申请号：US11303910

申请日：2005-12-19

申请人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

摘要： A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

摘要翻译： 提供了一种用于驱动相变存储器件的字线的方法和装置。 该方法可以包括在正常操作模式期间将未选择字线的第一电压电平和第二电压电平施加到所选择的字线，以及在备用操作模式期间将字线置于浮置状态。 相变存储装置可以包括用于驱动对应字线的多个字线驱动电路，其中多个字线驱动电路中的每一个包括驱动单元，该驱动单元将相应的字线设置为第一电压电平或第二电压电平 响应于第一控制信号，以及模式选择器，其根据相变存储器件的操作模式选择性地将第一电压电平施加到驱动单元。

公开(公告)号：US07417887B2

公开(公告)日：2008-08-26

申请号：US11303910

申请日：2005-12-19

申请人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

摘要： A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

摘要翻译： 提供了一种用于驱动相变存储器件的字线的方法和装置。 该方法可以包括在正常操作模式期间将未选择字线的第一电压电平和第二电压电平施加到所选择的字线，以及在备用操作模式期间将字线置于浮置状态。 相变存储装置可以包括用于驱动对应字线的多个字线驱动电路，其中多个字线驱动电路中的每一个包括驱动单元，该驱动单元将相应的字线设置为第一电压电平或第二电压电平 响应于第一控制信号，以及模式选择器，其根据相变存储器件的操作模式选择性地将第一电压电平施加到驱动单元。

公开(公告)号：US08179711B2

公开(公告)日：2012-05-15

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

公开(公告)号：US20090168493A1

公开(公告)日：2009-07-02

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00 ,  H01L21/00 ,  H01L47/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

公开(公告)号：US07453716B2

公开(公告)日：2008-11-18

申请号：US11238381

申请日：2005-09-29

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

公开(公告)号：US20070034908A1

公开(公告)日：2007-02-15

申请号：US11317292

申请日：2005-12-27

申请人： Woo-yeong Cho ,  Jong-soo Seo ,  Ik-chul Kim ,  Young-kug Moon

发明人： Woo-yeong Cho ,  Jong-soo Seo ,  Ik-chul Kim ,  Young-kug Moon

IPC分类号： H01L29/80

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  H01L27/2409 ,  H01L27/2436

摘要： A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.

摘要翻译： 相变随机存取存储器件包括连接到写电路和读电路的全局位线; 多个局部位线，每个位线连接到多个相变存储器单元; 以及选择性地将全局位线与多个局部位线中的每一个连接的多个列选择晶体管。 每个列选择晶体管具有取决于与写入电路和读取电路的距离的电阻。

公开(公告)号：US07633100B2

公开(公告)日：2009-12-15

申请号：US11317292

申请日：2005-12-27

申请人： Woo-yeong Cho ,  Jong-soo Seo ,  Ik-chul Kim ,  Young-kug Moon

发明人： Woo-yeong Cho ,  Jong-soo Seo ,  Ik-chul Kim ,  Young-kug Moon

IPC分类号： H01L29/80

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  H01L27/2409 ,  H01L27/2436

摘要： A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.

摘要翻译： 相变随机存取存储器件包括连接到写电路和读电路的全局位线; 多个局部位线，每个位线连接到多个相变存储器单元; 以及选择性地将全局位线与多个局部位线中的每一个连接的多个列选择晶体管。 每个列选择晶体管具有取决于与写入电路和读取电路的距离的电阻。

公开(公告)号：US20060200511A1

公开(公告)日：2006-09-07

申请号：US11363179

申请日：2006-02-28

申请人： Sung-woo Park ,  Jong-soo Seo ,  Hae-joo Jeong ,  Jong-seob Baek

发明人： Sung-woo Park ,  Jong-soo Seo ,  Hae-joo Jeong ,  Jong-seob Baek

IPC分类号： G06F7/38

CPC分类号： H04N5/211 ,  H04L25/03019 ,  H04L2025/03611 ,  H04L2025/03687 ,  H04L2025/03726 ,  H04N5/4401

摘要： A channel equalizer and a method of equalizing a channel. The channel equalizer includes a filter unit to filter an input training sequence signal and an input data signal according to a tap coefficient, a first multiplexer to calculate a priori error of each of the training sequence signal and the data signal, a decision unit to generate the training sequence signal and to soft-determine or hard-determine an output signal of the filter unit, an error signal generation unit to generate a priori error signal using an output signal of the decision unit and to generate an estimated posteriori error signal using the priori error signal, a first correction unit to correct a first adaptive step size algorithm using the signal input to the filter unit and the generated priori error signal and to correct a second adaptive step size algorithm using the signal input to the filter unit and the estimated posteriori error signal, and a second multiplexer to select one of the corrected first adaptive step size algorithm and the corrected second adaptive step size algorithm to be applied to the training sequence signal and the data signal, respectively.

摘要翻译： 信道均衡器和均衡信道的方法。 信道均衡器包括滤波器单元，用于根据抽头系数对输入的训练序列信号和输入数据信号进行滤波;第一多路复用器，用于计算每个训练序列信号和数据信号的先验误差;判定单元，用于产生 训练序列信号，并且软判定或硬确定滤波器单元的输出信号;误差信号生成单元，使用所述判定单元的输出信号产生先验误差信号，并使用所述估计后验误差信号 第一校正单元，用于使用输入到滤波器单元的信号和所产生的先验误差信号来校正第一自适应步长算法，并使用输入到滤波器单元的信号来校正第二自适应步长算法， 以及第二多路复用器，用于选择校正的第一自适应步长算法和校正后的第二自适应步骤之一 ep尺寸算法分别应用于训练序列信号和数据信号。

公开(公告)号：US07848165B2

公开(公告)日：2010-12-07

申请号：US12350344

申请日：2009-01-08

申请人： Chang-han Choi ,  Ho-keun Cho ,  Byung-gil Choi ,  Ki-sung Kim ,  Jong-chul Park ,  Jong-soo Seo

发明人： Chang-han Choi ,  Ho-keun Cho ,  Byung-gil Choi ,  Ki-sung Kim ,  Jong-chul Park ,  Jong-soo Seo

IPC分类号： G11C29/00

CPC分类号： G11C29/24 ,  G11C13/0004

摘要： A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column redundancy write drivers corresponds to at least one of the column redundancy cell arrays. The column redundancy write drivers are configured to transmit respective redundancy test data to the corresponding ones of the column redundancy cell arrays in response to a test control signal, which may be activated in response to each program pulse for writing data. Related test and access methods are also discussed.

摘要翻译： 相变随机存取存储器（PRAM）装置包括多个存储体，多个列冗余单元阵列和多个列冗余写入驱动器。 多个列冗余单元阵列中的每一个对应于至少一个存储体。 多个列冗余写入驱动器中的每一个对应于列冗余单元阵列中的至少一个。 列冗余写入驱动器被配置为响应于可以响应于用于写入数据的每个编程脉冲激活的测试控制信号将相应的冗余测试数据发送到列冗余单元阵列中的对应的冗余测试数据。 还讨论了相关的测试和访问方法。

公开(公告)号：US20090175072A1

公开(公告)日：2009-07-09

申请号：US12350344

申请日：2009-01-08

申请人： Chang-han Choi ,  Ho-keun Cho ,  Byung-gil Choi ,  Ki-sung Kim ,  Jong-chul Park ,  Jong-soo Seo

发明人： Chang-han Choi ,  Ho-keun Cho ,  Byung-gil Choi ,  Ki-sung Kim ,  Jong-chul Park ,  Jong-soo Seo

IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C29/00

CPC分类号： G11C29/24 ,  G11C13/0004

摘要： A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column redundancy write drivers corresponds to at least one of the column redundancy cell arrays. The column redundancy write drivers are configured to transmit respective redundancy test data to the corresponding ones of the column redundancy cell arrays in response to a test control signal, which may be activated in response to each program pulse for writing data. Related test and access methods are also discussed.

摘要翻译： 相变随机存取存储器（PRAM）装置包括多个存储体，多个列冗余单元阵列和多个列冗余写入驱动器。 多个列冗余单元阵列中的每一个对应于至少一个存储体。 多个列冗余写入驱动器中的每一个对应于列冗余单元阵列中的至少一个。 列冗余写入驱动器被配置为响应于可以响应于用于写入数据的每个编程脉冲激活的测试控制信号将相应的冗余测试数据发送到列冗余单元阵列中的对应的冗余测试数据。 还讨论了相关的测试和访问方法。