公开(公告)号：US08174878B2

公开(公告)日：2012-05-08

申请号：US13053471

申请日：2011-03-22

申请人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

发明人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

摘要翻译： 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元 外部提供的升压电压。

公开(公告)号：US08143653B2

公开(公告)日：2012-03-27

申请号：US12619016

申请日：2009-11-16

申请人： Woo-Yeong Cho ,  Jong-Soo Seo ,  Young-Kug Moon ,  Jun-Soo Bae ,  Kwang-Jin Lee

发明人： Woo-Yeong Cho ,  Jong-Soo Seo ,  Young-Kug Moon ,  Jun-Soo Bae ,  Kwang-Jin Lee

IPC分类号： H01L29/66

CPC分类号： G11C13/0064 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/72 ,  H01L27/2409 ,  H01L29/868 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

摘要翻译： 提供了相变随机存取存储器件。 相变随机存取存储器件包括连接到写入电路和读取电路的全局位线，每个连接到多个相变存储器单元的多个局部位线，以及选择性地连接全局位线的多个列选择晶体管 对于多个局部位线中的每一个，每个列选择晶体管具有根据其与写入电路和读取电路的距离而变化的电阻。

公开(公告)号：US08134866B2

公开(公告)日：2012-03-13

申请号：US12652842

申请日：2010-01-06

申请人： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

发明人： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

摘要： A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

摘要翻译： 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US07944741B2

公开(公告)日：2011-05-17

申请号：US12611606

申请日：2009-11-03

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

摘要翻译： 提供了使用相变存储器件的装置和系统。 相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多个复位线中相应的一个。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

公开(公告)号：US07907467B2

公开(公告)日：2011-03-15

申请号：US12873836

申请日：2010-09-01

申请人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

发明人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.

摘要翻译： 提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。 在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线 层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上设置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由 预定数量的子字线。 可以实现足够高集成度的有效的字线解码。

公开(公告)号：US20100329070A1

公开(公告)日：2010-12-30

申请号：US12873836

申请日：2010-09-01

申请人： Joon Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

发明人： Joon Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

IPC分类号： G11C8/10

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.

摘要翻译： 提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。 在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线 层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由 预定数量的子字线。 可以实现足够高集成度的有效的字线解码。

公开(公告)号：US07859882B2

公开(公告)日：2010-12-28

申请号：US11844511

申请日：2007-08-24

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2213/79

摘要： A resistive memory device is provided. The resistive memory device includes word lines arranged in M rows, bit lines arranged in N columns, local source lines arranged in M/2 rows, and resistive memory cells arranged in M rows and N columns. Each of the resistive memory cells includes a resistance variable element having a first electrode connected to a corresponding bit line, and a cell transistor having a first terminal connected to a second electrode of the resistance variable element, a second terminal connected to a corresponding local source line, and a control terminal connected to a corresponding word line. The local source line is commonly connected to the second terminals of the cell transistors of the two neighboring rows.

摘要翻译： 提供了一种电阻式存储器件。 电阻式存储装置包括排列成M行的字线，以N列排列的位线，以M / 2行排列的局部源极线以及布置成M行N列的电阻存储单元。 每个电阻存储单元包括电阻可变元件，电阻可变元件具有连接到对应的位线的第一电极，以及单元晶体管，其具有连接到电阻可变元件的第二电极的第一端子，连接到相应的本地源极的第二端子 线路和连接到相应字线的控制终端。 本地源极线通常连接到两个相邻行的单元晶体管的第二端子。

公开(公告)号：US07851878B2

公开(公告)日：2010-12-14

申请号：US12507504

申请日：2009-07-22

申请人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

摘要翻译： 磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体， 写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

公开(公告)号：US07843716B2

公开(公告)日：2010-11-30

申请号：US12031085

申请日：2008-02-14

申请人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

发明人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

IPC分类号： G11C5/02

CPC分类号： G11C7/067 ,  G11C5/025 ,  G11C5/04 ,  G11C7/062 ,  G11C8/10 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/063 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile memory device includes a stack-type memory cell array, a selection circuit and a read circuit. The memory cell array includes multiple memory cell layers and a reference cell layer, which are vertically laminated. Each of the memory cell layers includes multiple nonvolatile memory cells for storing data, and the reference cell layer includes multiple reference cells for storing reference data. The selection circuit selects a nonvolatile memory cell from the memory cell layers and at least one reference cell, corresponding to the selected nonvolatile memory cell, from the reference cell layer. The read circuit supplies a read bias to the selected nonvolatile memory cell and the selected reference cell corresponding to the selected nonvolatile memory cell, and reads data from the selected nonvolatile memory cell.

摘要翻译： 非易失性存储器件包括堆叠型存储单元阵列，选择电路和读取电路。 存储单元阵列包括垂直层叠的多个存储单元层和参考单元层。 每个存储单元层包括用于存储数据的多个非易失性存储单元，参考单元层包括用于存储参考数据的多个参考单元。 选择电路从参考单元层从存储单元层和对应于所选择的非易失性存储单元的至少一个参考单元选择非易失性存储单元。 读取电路向所选择的非易失性存储单元和与所选择的非易失性存储单元相对应的所选择的参考单元提供读偏置，并从所选择的非易失性存储单元读取数据。

公开(公告)号：US07791929B2

公开(公告)日：2010-09-07

申请号：US11902711

申请日：2007-09-25

申请人： Woo-yeong Cho ,  Yun-seung Shin

发明人： Woo-yeong Cho ,  Yun-seung Shin

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1655 ,  G11C11/1659 ,  Y10S977/935

摘要： A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

摘要翻译： 磁阻随机存取存储器（RAM）可以包括多个可变电阻器件，电连接到相应的可变电阻器件的多个读位线以及与读位线交替的多个写位线。 磁阻RAM可以被配置为当向第一可变电阻器件写入第一数据时，通过与第一可变电阻器件相邻的第一写入位线施加第一写入电流，并且将第一写入电流施加到与第一可写入位置相邻的第二写入位置 第二可变电阻器件，第二可变电阻器件与第一写入位线相邻，第一写入位线和第二写入位线之间以及第一写入电流和第一抑制电流沿相同的方向流动。