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    Phase change memory device and method of driving word line thereof
    1.
    发明申请
    Phase change memory device and method of driving word line thereof 有权
    相变存储器件及其驱动字线的方法

    公开(公告)号：US20060256612A1

    公开(公告)日：2006-11-16

    申请号：US11303910

    申请日：2005-12-19

    申请人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

    发明人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

    摘要： A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

    摘要翻译： 提供了一种用于驱动相变存储器件的字线的方法和装置。 该方法可以包括在正常操作模式期间将未选择字线的第一电压电平和第二电压电平施加到所选择的字线，以及在备用操作模式期间将字线置于浮置状态。 相变存储装置可以包括用于驱动对应字线的多个字线驱动电路，其中多个字线驱动电路中的每一个包括驱动单元，该驱动单元将相应的字线设置为第一电压电平或第二电压电平 响应于第一控制信号，以及模式选择器，其根据相变存储器件的操作模式选择性地将第一电压电平施加到驱动单元。

    Phase change memory device and method of driving word line thereof
    2.
    发明授权
    Phase change memory device and method of driving word line thereof 有权
    相变存储器件及其驱动字线的方法

    公开(公告)号：US07417887B2

    公开(公告)日：2008-08-26

    申请号：US11303910

    申请日：2005-12-19

    申请人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

    发明人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

    摘要： A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

    摘要翻译： 提供了一种用于驱动相变存储器件的字线的方法和装置。 该方法可以包括在正常操作模式期间将未选择字线的第一电压电平和第二电压电平施加到所选择的字线，以及在备用操作模式期间将字线置于浮置状态。 相变存储装置可以包括用于驱动对应字线的多个字线驱动电路，其中多个字线驱动电路中的每一个包括驱动单元，该驱动单元将相应的字线设置为第一电压电平或第二电压电平 响应于第一控制信号，以及模式选择器，其根据相变存储器件的操作模式选择性地将第一电压电平施加到驱动单元。

    Phase-change memory device
    3.
    发明授权
    Phase-change memory device 有权
    相变存储器件

    公开(公告)号：US07450415B2

    公开(公告)日：2008-11-11

    申请号：US11640956

    申请日：2006-12-19

    申请人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

    发明人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

    IPC分类号： G11C11/00

    CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

    摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.

    摘要翻译： 提供了相变存储器件。 相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第 多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及 行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

    Nonvolatile memory devices having enhanced bit line and/or word line driving capability
    4.
    发明申请
    Nonvolatile memory devices having enhanced bit line and/or word line driving capability 有权
    具有增强的位线和/或字线驱动能力的非易失性存储器件

    公开(公告)号：US20060215440A1

    公开(公告)日：2006-09-28

    申请号：US11348432

    申请日：2006-02-06

    申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

    发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5678 ,  G11C13/0004

    摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

    摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

    Nonvolatile memory devices having enhanced bit line and/or word line driving capability
    5.
    发明授权
    Nonvolatile memory devices having enhanced bit line and/or word line driving capability 有权
    具有增强的位线和/或字线驱动能力的非易失性存储器件

    公开(公告)号：US07397681B2

    公开(公告)日：2008-07-08

    申请号：US11348432

    申请日：2006-02-06

    申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

    发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

    IPC分类号： G11C27/00

    CPC分类号： G11C11/5678 ,  G11C13/0004

    摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

    摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

    Phase-change memory device
    6.
    发明申请
    Phase-change memory device 有权
    相变存储器件

    公开(公告)号：US20070153616A1

    公开(公告)日：2007-07-05

    申请号：US11640956

    申请日：2006-12-19

    申请人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

    发明人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

    IPC分类号： G11C11/00 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

    摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.

    摘要翻译： 提供了相变存储器件。 相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第 多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及 行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

    Writing driver circuit of phase-change memory
    7.
    发明授权
    Writing driver circuit of phase-change memory 有权

    公开(公告)号：US07012834B2

    公开(公告)日：2006-03-14

    申请号：US10829807

    申请日：2004-04-22

    申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

    Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory
    8.
    发明授权
    Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory 有权
    存储器系统，存储器件和装置，包括用于可变电阻存储器的写入驱动电路

    公开(公告)号：US07688621B2

    公开(公告)日：2010-03-30

    申请号：US11949299

    申请日：2007-12-03

    申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    IPC分类号： G11C11/00

    CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

    摘要： An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

    摘要翻译： 一种装置，非易失性存储装置和非易失性存储器系统包括易失性可变电阻存储器（VRM）单元阵列和具有脉冲选择电路，电流控制电路和电流驱动电路的写入驱动器电路。 电流控制电路接收偏置电压，当数据处于第一电平时，在复位脉冲的使能持续时间期间以第二电平输出控制信号，并且在该组的使能持续时间期间输出处于第一电平的控制信号 数据处于第二级时的脉冲。 当前驱动电路在复位脉冲或设定脉冲的使能期间内向相变存储器阵列输出写入电流。 写入驱动器电路可以根据数据的逻辑电平选择复位脉冲或设置脉冲，并根据复位脉冲或设定脉冲控制施加到相变存储器阵列的电流电平。

    Phase change random access memory
    9.
    发明授权
    Phase change random access memory 有权
    相变随机存取存储器

    公开(公告)号：US07548451B2

    公开(公告)日：2009-06-16

    申请号：US11896721

    申请日：2007-09-05

    申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

    发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

    摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

    摘要翻译： 提供了一种相变随机存取（PRAM）存储器。 PRAM可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，所述补偿单元被配置为向感测节点提供补偿电流以补偿减小 由流过多个相变存储器单元之一的电流引起的感测节点的电平，以及被配置为将感测节点的电平与参考电平进行比较并输出比较结果的感测放大器。

    Phase change random access memory
    10.
    发明申请
    Phase change random access memory 有权
    相变随机存取存储器

    公开(公告)号：US20080055972A1

    公开(公告)日：2008-03-06

    申请号：US11896721

    申请日：2007-09-05

    申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

    发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

    摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

    摘要翻译： 提供了一种相变随机存取（PRAM）存储器。 PRAM可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，所述补偿单元被配置为向感测节点提供补偿电流以补偿减小 由流过多个相变存储器单元之一的电流引起的感测节点的电平，以及被配置为将感测节点的电平与参考电平进行比较并输出比较结果的感测放大器。