公开(公告)号：US06212538B1

公开(公告)日：2001-04-03

申请号：US09143292

申请日：1998-08-28

申请人： Bernard Plessier

发明人： Bernard Plessier

IPC分类号： G06F700

CPC分类号： G06F7/768 ,  G06F7/535 ,  G06F7/72

摘要： A division method and division circuit that can be integrated into a modular arithmetic coprocessor performs a reversal by word for the dividend and the quotient. This is done using a plurality of registers.

摘要翻译： 可以集成到模​​数算术协处理器中的分割方法和分割电路通过单词对股息和商进行逆转。 这是使用多个寄存器完成的。

公开(公告)号：US5978295A

公开(公告)日：1999-11-02

申请号：US106941

申请日：1998-06-30

申请人： Alain Pomet ,  Bernard Plessier

发明人： Alain Pomet ,  Bernard Plessier

IPC分类号： G11C8/12 ,  G11C19/00

CPC分类号： G11C8/12 ,  G11C19/00

摘要： A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.

摘要翻译： 顺序访问存储器包括每个存储信息位的N个寄存器元素。 这些N个寄存器元件被分成每个包括L个元件的P组。 在其持续时间对应于时钟信号的P-1个连续周期的第一操作阶段中，仅激活每组的最后一个元件并进一步串联连接。 在其持续时间对应于时钟信号的单个周期的第二操作阶段中，所有元件被同时激活，元件组进一步串联连接。 其优点在于它能够降低存储器的动态消耗。

公开(公告)号：US07849255B2

公开(公告)日：2010-12-07

申请号：US10662225

申请日：2003-09-12

申请人： Bernard Plessier ,  Ming Kiat Yap

发明人： Bernard Plessier ,  Ming Kiat Yap

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C7/18 ,  G11C19/00 ,  G11C19/28 ,  G11C19/287

摘要： A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configurations. In a first operating configuration, the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, while in a second operating configuration the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array. A sub-array selector, responsive to a first memory address, selects one among the at least two sub-arrays according to the first memory address, and enables access to the selected sub-array. A memory element access circuit, responsive to a second memory address, enables access to a prescribed memory element in the selected sub-array after a prescribed number of shifts of the data content of the memory elements in the selected sub-array depending on the second memory address.

摘要翻译： 存储器包括存储器元件的至少一个阵列，至少一个阵列的划分成存储器元件的多个子阵列，以及阵列配置电路，用于选择性地将至少一个阵列放置在两种操作配置之一中 。 在第一操作配置中，所述至少一个阵列的存储器元件彼此耦合以形成一维顺序可访问的存储器，而在第二操作配置中，每个子阵列中的存储器元件彼此耦合，以便 为了形成独立的单维顺序可访问的存储块，子阵列的任何存储元件的数据内容可以通过移位通过子阵列的存储元件来旋转。 响应于第一存储器地址的子阵列选择器根据第一存储器地址在所述至少两个子阵列中选择一个，并使能够访问所选择的子阵列。 存储器元件访问电路响应于第二存储器地址，使得能够在所选择的子阵列中的存储元件的数据内容的规定数量的移位之后，根据第二存储器地址访问所选择的子阵列中的规定的存储器元件 内存地址。

公开(公告)号：US20080123841A1

公开(公告)日：2008-05-29

申请号：US10531843

申请日：2002-10-21

申请人： Bernard Plessier

发明人： Bernard Plessier

IPC分类号： H04L9/28

CPC分类号： H04L9/0643 ,  H04L2209/04 ,  H04L2209/12

摘要： An apparatus arranged to accept digital data as an input and to process the data according to one of either the Secure Hash Algorithm (SHA-1) or Message Digest (MD5) algorithm to produce a fixed length output word. The apparatus includes a plurality of rotational registers for storing data, one of the registers arranged to receive the input data, and data stores for initialization of some of the plurality of registers according to whether the SHA-1 or MD5 algorithm is used. The data stores include fixed data relating to SHA-1 and MD5 operation. Also included is a plurality of dedicated combinatorial logic circuits arranged to perform logic operations on data stored in selected ones of the plurality of registers.

摘要翻译： 一种被设置为接受数字数据作为输入并根据安全散列算法（SHA-1）或消息摘要（MD5）算法之一来处理数据以产生固定长度输出字的装置。 该装置包括用于存储数据的多个旋转寄存器，用于接收输入数据的寄存器之一，以及根据是使用SHA-1还是MD5算法初始化多个寄存器中的一些的数据存储。 数据存储包括与SHA-1和MD5操作有关的固定数据。 还包括多个专用组合逻辑电路，其被布置为对存储在多个寄存器中的选定寄存器中的数据执行逻辑运算。

公开(公告)号：US06275837B1

公开(公告)日：2001-08-14

申请号：US09244217

申请日：1999-02-04

申请人： Bernard Plessier

发明人： Bernard Plessier

IPC分类号： G06F700

CPC分类号： G06F7/728

摘要： A Pfield operation defined according to the Montgomery method by Pfield(A, B)N=A*B*I mod N, where I is a determinable error, is implemented in a processor. The least significant word of the data elements A and N which are stored in elementary sub-registers are shifted twice. This eliminates delay cells in a processor used for executing the Pfield operation.

摘要翻译： 在处理器中实现根据Pfield（A，B）的蒙哥马利方法定义的Pfield操作N = A * B * I mod N，其中I是可确定的误差。 存储在基本子寄存器中的数据元素A和N的最低有效字被移位两次。 这消除了用于执行Pfield操作的处理器中的延迟单元。

公开(公告)号：US07649990B2

公开(公告)日：2010-01-19

申请号：US10531843

申请日：2002-10-21

申请人： Bernard Plessier ,  Ming-Kiat Yap

发明人： Bernard Plessier ,  Ming-Kiat Yap

IPC分类号： H04L9/32 ,  H04K1/00 ,  H04L9/00 ,  H04L1/00 ,  H03K17/16 ,  H03K19/003

CPC分类号： H04L9/0643 ,  H04L2209/04 ,  H04L2209/12

摘要： An apparatus arranged to accept digital data as an input and to process the data according to one of either the Secure Hash Algorithm (SHA-1) or Message Digest (MD5) algorithm to produce a fixed length output word. The apparatus includes a plurality of rotational registers for storing data, one of the registers arranged to receive the input data, and data stores for initialization of some of the plurality of registers according to whether the SHA-1 or MD5 algorithm is used. The data stores include fixed data relating to SHA-1 and MD5 operation. Also included is a plurality of dedicated combinatorial logic circuits arranged to perform logic operations on data stored in selected ones of the plurality of registers.

摘要翻译： 一种被设置为接受数字数据作为输入并根据安全散列算法（SHA-1）或消息摘要（MD5）算法之一来处理数据以产生固定长度输出字的装置。 该装置包括用于存储数据的多个旋转寄存器，用于接收输入数据的寄存器之一，以及根据是使用SHA-1还是MD5算法初始化多个寄存器中的一些的数据存储。 数据存储包括与SHA-1和MD5操作有关的固定数据。 还包括多个专用组合逻辑电路，其被布置为对存储在多个寄存器中的选定寄存器中的数据执行逻辑运算。

公开(公告)号：US06542413B1

公开(公告)日：2003-04-01

申请号：US09491428

申请日：2000-01-26

申请人： Bernard Plessier ,  Alain Pomet

发明人： Bernard Plessier ,  Alain Pomet

IPC分类号： G11C700

CPC分类号： G11C7/103 ,  G06F7/728 ,  H03M9/00

摘要： A storage device is provided. The storage device includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. In a preferred embodiment, a control circuit is coupled to the address bus, with the control circuit including address registers for storing as many address pointers as the number of k-bit shift registers. Also provided is a coprocessor of the type that includes a series input terminal, a series output terminal, and computation elements located on at least one data path between the series input terminal and the series output terminal. Further, an IC chip card that includes a microprocessor, storage, and a coprocessor is provided.

摘要翻译： 提供存储设备。 存储装置包括具有并行数据总线和并行地址总线的至少一个存储器; 具有并行输入和并行输出的第一k位锁存电路，并行输入连接到数据总线; 具有并行输入和串联输出的第一k位移位寄存器，并行输入连接到第一锁存电路的输出; 具有并行输入和并行输出的第二k位锁存电路，并行输出连接到数据总线; 以及具有串联输入和并行输出的第二k位移位寄存器，并联输出连接到第二锁存电路的输入。 在优选实施例中，控制电路耦合到地址总线，其中控制电路包括用于存储与k位移位寄存器数目一样多的地址指针的地址寄存器。 还提供了一种类型的协处理器，其包括串联输入端子，串联输出端子和位于串联输入端子和串联输出端子之间的至少一个数据路径上的计算元件。 此外，提供了包括微处理器，存储器和协处理器的IC芯片卡。

公开(公告)号：US5963505A

公开(公告)日：1999-10-05

申请号：US105560

申请日：1998-06-26

申请人： Alain Pomet ,  Bernard Plessier

发明人： Alain Pomet ,  Bernard Plessier

IPC分类号： G11C8/12 ,  G11C19/00 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C19/00

摘要： A sequential access memory working at the rate of a clock signal CK includes N register elements N, each storing an information bit. These register elements are divided into L groups, each comprising P elements that are series-connected and simultaneously activated or not activated (with P.times.L=N). The register elements of a given group are activated at least P times consecutively during a part of the time, and are not activated for the rest of the time. Accordingly, each group stores P consecutive information bits each from among the N bits arriving in serial form at the input of the memory. The advantage of the memory is that it enables a reduction in the dynamic energy consumption.

摘要翻译： 以时钟信号CK的速率工作的顺序存取存储器包括N个寄存器元件N，每个寄存器元件存储信息位。 这些寄存器元件分为L组，每组包括串联连接并同时激活或未激活的P元素（PxL = N）。 给定组的寄存器元件在一段时间内连续至少P次激活，并且在其余时间内不被激活。 因此，每个组在存储器的输入处以串行形式到达的N个比特中存储P个连续的信息比特。 存储器的优点在于其能够降低动态能量消耗。

公开(公告)号：US07715551B2

公开(公告)日：2010-05-11

申请号：US10835102

申请日：2004-04-29

申请人： Bernard Plessier

发明人： Bernard Plessier

IPC分类号： H04L9/00

CPC分类号： H04L9/3066 ,  G06F7/728 ,  H04L2209/122

摘要： A cryptographic system comprising: 1) a first Montgomery-based cryptographic engine that receives a first operand and a second operand and generates a first result and 2) a second Montgomery-based cryptographic engine that receives a first reduced operand derived from the first operand and a second reduced operand derived from the second operand and generates a second result. The second Montgomery-based cryptographic engine operates in parallel with the first Montgomery-base cryptographic engine. The cryptographic system further comprises a comparator for comparing the second result to a first reduced result derived from the first result and generating an error flag if the second result and the first reduced result are different.

摘要翻译： 一种加密系统，包括：1）第一基于蒙哥马利的密码引擎，其接收第一操作数和第二操作数并产生第一结果;以及2）第二蒙哥马利密码引擎，其接收从所述第一操作数导出的第一简化操作数， 从第二操作数导出的第二缩减操作数并产生第二结果。 第二个基于Montgomery的加密引擎与第一个蒙哥马利加密引擎并行运行。 密码系统还包括比较器，用于将第二结果与从第一结果导出的第一缩减结果进行比较，并且如果第二结果和第一缩减结果不同则产生错误标志。

公开(公告)号：US07319758B2

公开(公告)日：2008-01-15

申请号：US09727300

申请日：2000-11-30

申请人： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

发明人： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

IPC分类号： H04L9/00 ,  G06F11/30 ,  G06F1/04 ,  G06F3/00

CPC分类号： H04L9/0891 ,  H04L9/0631 ,  H04L2209/04

摘要： In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

摘要翻译： 在包括双向总线的电子部件中，数据元件通过该双向总线以时钟信号的速率在外围设备和中央处理单元之间行进，中央处理单元和至少一个外围设备都包括数据加密/解密单元。 每个数据加密/解密单元使用相同的秘密密钥。 秘密密钥是从与时钟信号同步的随机信号在每个小区中的每个时钟周期本地产生的，并且通过单向传输线应用于每个小区。