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    Modified adder tree structure and method using logic and gates to generate carry-in values
    5.
    发明授权
    Modified adder tree structure and method using logic and gates to generate carry-in values 有权
    改进的加法器树结构和方法使用逻辑和门来生成进位值

    公开(公告)号：US6127842A

    公开(公告)日：2000-10-03

    申请号：US344912

    申请日：1999-06-24

    申请人： Parin B. Dalal ,  Steve Hale ,  Stephen C. Purcell ,  Nital Patwa

    发明人： Parin B. Dalal ,  Steve Hale ,  Stephen C. Purcell ,  Nital Patwa

    IPC分类号： G06F7/50 ,  G06F7/52 ,  G06F7/60 ,  H03K19/173

    CPC分类号： G06F7/5318 ,  G06F7/509 ,  G06F7/607

    摘要： In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND's the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.

    摘要翻译： 根据本发明，加法器树结构包括至少两个加法器级。 在根据本发明的电路和方法中，两个加法器级中的第一个产生公共权重的两个比特和比公共权重的两个比特重一比特的权重的其他更高有效比特。 两个加法器级中的第二级包括一个加法器，其接收在两个加法器级中的第一级中产生的更高有效位。 第二加法器级还包括与门，其接收和逻辑与公共权重的两个比特以在第二级中产生加法器的进位位。 上述加法器树结构和附加方法具有允许加法器的更多输入端子包含关于加法器树结构的输入值的信息的优点。 因此，加法器被更有效地使用，并且需要较少的加法器来执行特定的功能。