公开(公告)号：US07663192B2

公开(公告)日：2010-02-16

申请号：US12215989

申请日：2008-06-30

申请人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel Aubertine

发明人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel Aubertine

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/66628 ,  H01L29/7834

摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。 晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134） 绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。 所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

公开(公告)号：US20140264280A1

公开(公告)日：2014-09-18

申请号：US13996848

申请日：2013-03-15

申请人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.

摘要翻译： 本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤 过程。 当用于制造源结构的材料和漏极结构易于被用于去除牺牲材料的工艺被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和排出结构，即低 选择性地连接到源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源结构形成的触点之间的电位短路以及漏极结构。

公开(公告)号：US09064944B2

公开(公告)日：2015-06-23

申请号：US13996848

申请日：2013-03-15

申请人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC分类号： H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

摘要翻译： 本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤 过程。 当在源结构和/或漏极结构的制造中使用的材料易于被用于去除牺牲物的过程被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和/或排出结构 材料，即选择性地低至源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源极结构和/或漏极结构形成的触点之间的电位短路。