利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

35 条记录 (耗时 0.019 秒)

    NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS
    1.
    发明申请
    NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS 有权
    具有下层蚀刻层的纳米晶体管

    公开(公告)号：US20140264280A1

    公开(公告)日：2014-09-18

    申请号：US13996848

    申请日：2013-03-15

    申请人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

    发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

    IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

    摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.

    摘要翻译： 本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤 过程。 当用于制造源结构的材料和漏极结构易于被用于去除牺牲材料的工艺被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和排出结构，即低 选择性地连接到源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源结构形成的触点之间的电位短路以及漏极结构。

    Nanowire transistor with underlayer etch stops
    2.
    发明授权
    Nanowire transistor with underlayer etch stops 有权
    具有底层蚀刻的纳米线晶体管停止

    公开(公告)号：US09064944B2

    公开(公告)日：2015-06-23

    申请号：US13996848

    申请日：2013-03-15

    申请人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

    发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

    IPC分类号： H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

    摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

    摘要翻译： 本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤 过程。 当在源结构和/或漏极结构的制造中使用的材料易于被用于去除牺牲物的过程被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和/或排出结构 材料，即选择性地低至源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源极结构和/或漏极结构形成的触点之间的电位短路。

    LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS
    3.
    发明申请
    LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS 有权
    纳米晶体管的漏电减少结构

    公开(公告)号：US20140264253A1

    公开(公告)日：2014-09-18

    申请号：US13996845

    申请日：2013-03-14

    申请人： Seiyon Kim ,  Kelin Kuhn ,  Rafael Rios ,  Mark Armstrong

    发明人： Seiyon Kim ,  Kelin Kuhn ,  Rafael Rios ,  Mark Armstrong

    IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/266 ,  H01L29/10 ,  H01L21/265

    CPC分类号： H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

    摘要： A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.

    摘要翻译： 本描述的纳米线器件可以包括形成在至少一个纳米线晶体管和其上形成纳米线晶体管的微电子衬底之间的高度掺杂的底层，其中高度掺杂的底层可以减少或基本上消除可能发生的泄漏和高栅极电容 在纳米线晶体管的栅极结构的底部。 由于高掺杂底层的形成可能导致在纳米线晶体管的源极结构和漏极结构之间的界面处的栅极感应漏极泄漏，可以在高掺杂底层和纳米线晶体管之间形成未掺杂或低掺杂材料的薄层 。