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公开(公告)号：US4696019A
公开(公告)日：1987-09-22
申请号：US652028
申请日：1984-09-19
CPC分类号： G06F11/187 , G06F11/1679 , G06F11/1691 , G06F11/1604
摘要： A synchronizer for use in synchronizing individual signal processors in a multi-channel system is disclosed. Each synchronizer has a counter for counting its associated processor's clock pulses and, upon reaching a selected count, providing a counter frame output signal at an output thereof for use by each of the other synchronizers in the system. Each synchronizer has a voter responsive to counter output signals from each of the other synchronizers, and from itself as well, at input ports thereof. Each synchronizer's voter provides a frame sync (macro sync) pulse in each counter frame after receiving a selected number of counter frame output signals from any of the synchronizers in the system. Each synchronizer's voted frame sync pulse is provided at an output port of the sychronizer and may be utilized, depending on the application, for routing back into the synchronizer at a frame sync input port for resetting the synchronizer's own counter, or, when used as a master, for routing to one or more (slave) synchronizers for the same purpose. Each synchronizer's voter includes a rising edge voter that arms a falling edge voter only during a selected portion of the expected counter frame period (voting window). The synchronizer voter architecture can include clocked latches or not. The synchronizer may include fast and slow clock detectors. The synchronizer interfaces with its associated processor and includes disable circuitry for permitting the CPU to disable nonfunctional frame sync signals.
摘要翻译： 公开了一种用于同步多通道系统中的各个信号处理器的同步器。 每个同步器具有用于对其相关联的处理器的时钟脉冲进行计数的计数器，并且在达到选定的计数时，在其输出端提供计数器帧输出信号，供系统中的每个其他同步器使用。 每个同步器具有响应于来自每个其他同步器的输出信号的选择器，并且在其输入端口处也自己。 每个同步器的选择器在从系统中的任何同步器接收到选定数量的计数器帧输出信号之后，在每个计数器帧中提供帧同步（宏同步）脉冲。 每个同步器的投票帧同步脉冲被提供在同步器的输出端口处，并且可以根据应用利用在用于重置同步器自己的计数器的帧同步输入端口处的路由回到同步器中，或者当被用作 主站，用于路由到一个或多个（从站）同步器，用于相同的目的。 每个同步器的选民都包括一个上升的投票者，只能在期望的计数器帧周期的选定部分（投票窗口）中控制下降投票者。 同步器选择器架构可以包括时钟锁存器。 同步器可以包括快速和慢速时钟检测器。 同步器与其相关联的处理器接口，并且包括禁止电路，用于允许CPU禁用非功能帧同步信号。
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2.发明授权System for loading a boot program into an initially blank programmable memory of a microprocessor using state machine and serial bus 失效将引导程序加载到使用状态机和串行总线的微处理器的初始空白可编程存储器中的系统
公开(公告)号：US5652886A
公开(公告)日：1997-07-29
申请号：US317975
申请日：1994-10-03
申请人： Bhalchandra R. Tulpule , Mark A. Foss , Edward J. Kysar, III , Edward M. Oscarson , Leonard Spain , Michael C. Crisafulli
发明人： Bhalchandra R. Tulpule , Mark A. Foss , Edward J. Kysar, III , Edward M. Oscarson , Leonard Spain , Michael C. Crisafulli
CPC分类号： G06F9/4403
摘要： A state machine has specific states to boot a microprocessor and retrieve data from the microprocessor's memories while the microprocessor is running, but with operation temporarily suspended under control of the state machine. The state machine is programmed after it is installed on a circuit board with the microprocessor. The state machine is connected to a standard bus and through its specific states provides an interface to the microprocessor as well as the instructions for booting the microprocessor when the microprocessor is powered up.
摘要翻译： 状态机具有启动微处理器并在微处理器运行时从微处理器的存储器检索数据的具体状态，但是在状态机的控制下暂时停止操作。 状态机在与微处理器安装在电路板上之后进行编程。 状态机连接到标准总线，并且通过其特定状态提供微处理器的接口以及当微处理器通电时用于引导微处理器的指令。
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3.发明授权
公开(公告)号：US5128943A
公开(公告)日：1992-07-07
申请号：US346247
申请日：1989-04-05
CPC分类号： G05B9/03 , G06F11/1666 , G06F11/1487 , G06F11/20
摘要： An interrupt is provided to a signal processor having a non-maskable interrupt input, in response to the detection of a request for transfer to backup software. The signal processor provides a transfer signal to a transfer mechanism only after completion of the present machine cycle. Transfer to the backup software is initiated by the transfer mechanism only upon reception of the transfer signal.
摘要翻译： 响应于检测到传送到备份软件的请求，向具有不可屏蔽中断输入的信号处理器提供中断。 信号处理器仅在本机循环完成之后才向传送机构提供传送信号。 只有在接收到传送信号时，传输机制才能启动传输到备份软件。
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公开(公告)号：US4980824A
公开(公告)日：1990-12-25
申请号：US298291
申请日：1989-01-17
CPC分类号： G06F9/4881 , G06F9/4436 , G06F9/5038 , G06F2209/483 , G06F2209/484 , G06F2209/5017 , G06F2209/506
摘要： Tasks may be planned for execution on a single processor or are split up by the designer for execution among a plurality of signal processors. The tasks are modeled using a design aid called a precedence graph, from which a dependency table and a prerequisite table are established for reference within each processor. During execution, at the completion of a given task, an end of task interrupt is provided from any processor which has completed a task to any and all other processors including itself in which completion of that task is a prerequisite for commencement of any dependent tasks. The relevant updated data may be transferred by the processor either before or after signalling task completion to the processors needing the updated data prior to commencing execution of the dependent tasks. Coherency may be ensured, however, by sending the data before the interrupt. When the end of task interrupt is received in a processor, its dependency table is consulted to determine those tasks dependent upon completion of the task which has just been signalled as completed, and task dependency signals indicative thereof are provided and stored in a current status list of a prerequisite table. The current status of all current prerequisites are compared to the complete prerequisites listed for all affected tasks and those tasks for which the comparison indicates that all prerequisites have been met are queued for execution in a selected order.
摘要翻译： 任务可以被计划在单个处理器上执行，或被设计者拆分以在多个信号处理器之间执行。 使用称为优先图的设计辅助来对任务进行建模，从中建立依赖关系表和前提表以供每个处理器内的参考。 在执行期间，在给定任务完成时，从已经完成任务到任何和所有其他处理器的任何处理器提供任务中断的结束，包括其中完成该任务是开始任何从属任务的先决条件。 相关的更新数据可以在信令任务完成之前或之后由处理器传送到在开始执行依赖任务之前需要更新的数据的处理器。 然而，可以通过在中断之前发送数据来确保一致性。 当在处理器中接收到任务中断的结束时，查询其依赖关系表以确定那些刚刚完成信号完成的任务，并且指示它们的任务依赖信号被提供并存储在当前状态列表中 的前提表。 将所有当前先决条件的当前状态与为所有受影响的任务列出的完整先决条件进行比较，并且比较指示所有先决条件已满足的任务排队等待以选定顺序执行。
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5.发明授权Watchdog activity monitor (WAM) for use wth high coverage processor self-test 失效Watchdog活动监视器（WAM）用于高覆盖处理器自检
公开(公告)号：US4727549A
公开(公告)日：1988-02-23
申请号：US758251
申请日：1985-09-13
IPC分类号： G06F11/00 , G06F11/07 , G06F11/267
CPC分类号： G06F11/2236 , G06F11/0721 , G06F11/0751 , G06F11/0757 , G06F11/076
摘要： A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor's clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.
摘要翻译： 公开了用户环境中信号处理器的高故障覆盖，指令建模自检。 自检执行一系列子测试，并在执行每个子测试时发出状态转换信号。 自检可以与看门狗活动监视器（WAM）组合，该监视器活动监视器（WAM）在存在与预期号码不一致的计数数量状态转换的情况下提供测试失败信号。 可以在WAM中提供独立的时间测量，以通过检查处理器的时钟来增加故障覆盖。 此外，冗余处理器系统可以避免使用独特的未选择的布防技术和装置无意中取消切断的处理器。
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6.发明授权Interface having receive and transmit message label memories for providing communication between a host computer and a bus 失效接口具有用于在主计算机和总线之间提供通信的接收和发送消息标签存储器
公开(公告)号：US5617544A
公开(公告)日：1997-04-01
申请号：US363604
申请日：1994-12-23
CPC分类号： G06F13/4217
摘要： An interface between a host and a bus includes label generator and a memory. The label generator responds to bus label signals from the bus, for providing label signals. The memory responds to bus signals from the bus, for providing memory host signals to the bus. The memory further reponds to the label signals from the label generator for storing the label signals as label memory signals. The memory further responds to host signals from the host, either for providing memory bus signals to the host when the host reads memory bus information from the memory, or for providing said label memory signals to the host when the host reads label memory information from the memory.
摘要翻译： 主机和总线之间的接口包括标签发生器和存储器。 标签发生器响应来自总线的总线标签信号，用于提供标签信号。 存储器响应来自总线的总线信号，用于向总线提供存储器主机信号。 存储器进一步回复来自标签发生器的标签信号，用于将标签信号存储为标签存储信号。 存储器还响应来自主机的主机信号，用于当主机从存储器读取存储器总线信息时向主机提供存储器总线信号，或者当主机从主机从主机读取标签存储器信息时向主机提供标签存储器信号 记忆。
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7.发明授权Apparatus for interfacing between at least one channel and at least one bus 失效用于在至少一个通道和至少一个总线之间进行接口的设备
公开(公告)号：US4625307A
公开(公告)日：1986-11-25
申请号：US681172
申请日：1984-12-13
IPC分类号： G06F11/20 , G06F11/267 , G06F13/28 , G06F13/40 , H04J3/00
CPC分类号： G06F11/2005 , G06F11/2007 , G06F11/2236 , G06F13/28 , G06F13/4027
摘要： A coherent interface between one or more asynchronous busses and one or more channels in which only one channel is permitted to communicate with a bus at a time is disclosed.
摘要翻译： 公开了一个或多个异步总线和一个或多个通道之间的相干接口，其中一次只允许一个通道与总线通信。
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公开(公告)号：US4771427A
公开(公告)日：1988-09-13
申请号：US914698
申请日：1986-10-02
CPC分类号： G06F11/1658 , G06F11/184 , G06F11/182
摘要： A miscomparison between a channel's configuration data base and a voted system configuration data base in a redundant channel system having identically operating, frame synchronous channels triggers autoequalization of the channel's historical signal data bases in a hierarchical, chronological manner with that of a correctly operating channel. After equalization, symmetrization of the channel's configuration data base with that of the system permits upgrading of the previously degraded channel to full redundancy. An externally provided equalization command, e.g., manually actuated, can also trigger equalization.
摘要翻译： 在具有相同操作的帧同步信道的冗余信道系统中，信道的配置数据库和被投票系统配置数据库之间的错误，以与正确操作的信道的等级，时间顺序的方式触发信道的历史信号数据库的自动均衡。 均衡后，通道的配置数据库与系统的配置数据库的对称性允许先前退化的通道升级到完全冗余。 外部提供的均衡命令，例如手动启动，也可以触发均衡。
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公开(公告)号：US4623997A
公开(公告)日：1986-11-18
申请号：US681166
申请日：1984-12-13
CPC分类号： H04L12/5693 , G06F13/28 , G06F13/4027 , G06F13/423 , H04L47/562 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9084
摘要： An interface for use between an asynchronous bus and a signal processor is disclosed. The interface utilizes both a wraparound receive and transmit memory to ensure coherency with very little processor overhead.
摘要翻译： 公开了一种用于异步总线和信号处理器之间的接口。 该接口利用环绕接收和发送存储器来确保非常少的处理器开销的一致性。
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公开(公告)号：US4139899A
公开(公告)日：1979-02-13
申请号：US733055
申请日：1976-10-18
摘要： In a network for transferring a source field in a source word into a destination field in a destination word two basic hardware sub-functions are utilized: rotation and mask vector generation. In the network the destination field of a destination word is masked. Concurrently in the network, a source word is rotated bringing the source field thereof into corresponding alignment with the masked destination field and all but the source field of the source word is masked. Subsequent logical combining of the masked destination word and the rotated and masked source word generates the desired field transference. In one embodiment the required masking operation is accomplished during a single pass of the destination and source words through the network. In an alternate embodiment using less masking hardware only half of the required masking is accomplished during each pass and two passes are required before the logical combining to achieve the desired field transference.
摘要翻译： 在用于将源字中的源字段传送到目的地字中的目的字段的网络中，使用两个基本硬件子功能：旋转和掩码向量生成。 在网络中，目的地字的目标字段被屏蔽。 同时在网络中，源字被旋转，使其源字段与掩蔽的目的地字段相对应，并且源字符的源字段除外都被掩蔽。 掩蔽的目的地字和旋转和屏蔽的源字之后的逻辑组合产生所需的字段转移。 在一个实施例中，所需的掩蔽操作在目的地和源字通过网络的单次通过期间完成。 在使用较少掩蔽硬件的替代实施例中，仅在所需屏蔽期间完成所需屏蔽的一半，并且在逻辑组合之前需要两遍以实现期望的场传输。
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