公开(公告)号：US08239794B2

公开(公告)日：2012-08-07

申请号：US12568985

申请日：2009-09-29

申请人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

发明人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5022

摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.

摘要翻译： 公开了用于估计电子电路的漏电流的系统和相关方法的实施例。 实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络） 并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。 然后，使用该信息，实施例估计电子电路的漏电流。 这是通过首先确定每个受驱动网络边界分区的每个状态的驱动网络边界分区的泄漏电流以及在电子电路运行期间该状态将在该被驱动的有界分区中发生的概率来实现的。 然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。 然后汇总结果。

公开(公告)号：US07487480B1

公开(公告)日：2009-02-03

申请号：US12118857

申请日：2008-05-12

申请人： Bhavna Agrawal ,  David J. Hathaway ,  Peng Peng

发明人： Bhavna Agrawal ,  David J. Hathaway ,  Peng Peng

IPC分类号： G06F17/50 ,  G06F17/17 ,  G06F17/11

CPC分类号： G06F17/5036

摘要： A method of estimating a leakage for a plurality of transistors in an integrated circuit that accounts for narrow channel effects includes determining an expected total leaking transistor width for the collection; determining an expected total number of leaking transistors for the collection; determining an average width of a leaking transistor from the expected total leaking transistor width and expected total number of leaking transistors; estimating a leakage for a transistor of the average width; and determining the estimated leakage for the collection of transistors by multiplying the leakage for a transistor of the average width by the expected total number of leaking transistors for the collection.

摘要翻译： 估计考虑窄通道效应的集成电路中的多个晶体管的泄漏的方法包括确定用于采集的预期的总泄漏晶体管宽度; 确定用于收集的泄漏晶体管的预期总数; 从预期的总泄漏晶体管宽度和预期的泄漏晶体管总数确定泄漏晶体管的平均宽度; 估计平均宽度的晶体管的泄漏; 并且通过将用于平均宽度的晶体管的泄漏乘以用于集合的预期泄漏晶体管总数来确定用于收集晶体管的估计泄漏。

公开(公告)号：US20110077882A1

公开(公告)日：2011-03-31

申请号：US12568985

申请日：2009-09-29

申请人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

发明人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

IPC分类号： G06F19/00 ,  G01R27/00

CPC分类号： G06F17/5022

摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.

摘要翻译： 公开了用于估计电子电路的漏电流的系统和相关方法的实施例。 实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络） 并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。 然后，使用该信息，实施例估计电子电路的漏电流。 这是通过首先确定每个受驱动网络边界分区的每个状态，驱动网络边界分区的泄漏电流以及在电子电路运行期间状态将在驱动网络划分区域内发生的概率来实现的。 然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。 然后汇总结果。

公开(公告)号：US20120266119A1

公开(公告)日：2012-10-18

申请号：US13088688

申请日：2011-04-18

申请人： Jeffrey P. Soreff ,  Bhavna Agrawal ,  David J. Hathaway

发明人： Jeffrey P. Soreff ,  Bhavna Agrawal ,  David J. Hathaway

IPC分类号： G06F9/455

CPC分类号： G06F17/5031

摘要： A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.

摘要翻译： 一种用于构建延迟规则的方法，其中包括MIS模拟对静态时序分析的影响，降低成本。 本方法包括构建歪斜窗口，用于纯粹来自SIS数据的MIS惩罚，并根据使用案例中的倾斜度接近偏斜窗口的边缘来缩小规则使用期间的MIS惩罚。 该方法既适用于电路库的定时规则构造，也适用于宏的定时规则构造，其中宏中仅部分电路可能对宏输入之间的偏移敏感。

公开(公告)号：US08607176B2

公开(公告)日：2013-12-10

申请号：US13088688

申请日：2011-04-18

申请人： Jeffrey P. Soreff ,  Bhavana Agrawal ,  David J. Hathaway

发明人： Jeffrey P. Soreff ,  Bhavana Agrawal ,  David J. Hathaway

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.

摘要翻译： 一种用于构建延迟规则的方法，其中包括MIS模拟对静态时序分析的影响，降低成本。 本方法包括构建歪斜窗口，用于纯粹来自SIS数据的MIS惩罚，并根据使用案例中的倾斜度接近偏斜窗口的边缘来缩小规则使用期间的MIS惩罚。 该方法既适用于电路库的定时规则构造，也适用于宏的定时规则构造，其中宏中仅部分电路可能对宏输入之间的偏移敏感。

公开(公告)号：US08381150B2

公开(公告)日：2013-02-19

申请号：US13151295

申请日：2011-06-02

申请人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

发明人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F8/20 ,  G06F2217/84

摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.

摘要翻译： 描述了一种用于定时图的有效多线程分析的方法。 该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。 为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。 使用一个父计算线程和多个子线程。 父计算线程识别用于分析的任务，并在子线程之间分配它们。 每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。 完成分析后，子线程将结果传回主时序图，等待下一个任务。 由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。 每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。 访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

公开(公告)号：US08056038B2

公开(公告)日：2011-11-08

申请号：US12354360

申请日：2009-01-15

申请人： Kerim Kalafala ,  Hemlata Gupta ,  David J. Hathaway ,  Jeffrey G. Hemmett

发明人： Kerim Kalafala ,  Hemlata Gupta ,  David J. Hathaway ,  Jeffrey G. Hemmett

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.

摘要翻译： 在边界到达时间，转数，所需到达时间或负载与检查点运行不同的环境中加载检查点定时的方法。 为一个或多个分层模块生成的定时检查点文件，在此期间为每个输入分配唯一的相位标签。 独特相位标签的关联允许随后的重新启动分析以有效地调整与重启定时环境相关的检查点定时。 在重新启动运行中，读取一个或多个这样的检查点文件，在此期间，执行到达的初始传播，所需到达和转换时间，然后基于调整的到达时间和所需的到达时间进行本地重新更新。 最后，如果更新了多个分级模块，则基于松弛变化阈值执行定时值的全局重新计算，以便确定是否引入了任何新的定时故障。

公开(公告)号：US08056035B2

公开(公告)日：2011-11-08

申请号：US12132636

申请日：2008-06-04

申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.

摘要翻译： 执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。 另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容 净对。 此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。

公开(公告)号：US08015526B2

公开(公告)日：2011-09-06

申请号：US12138871

申请日：2008-06-13

申请人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

发明人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

公开(公告)号：US07890906B2

公开(公告)日：2011-02-15

申请号：US12117761

申请日：2008-05-09

申请人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

发明人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

摘要翻译： 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。