公开(公告)号：US20050140417A1

公开(公告)日：2005-06-30

申请号：US10751135

申请日：2003-12-30

申请人： Bheem Patel ,  Ming Zeng ,  Tsung-Chuan Whang

发明人： Bheem Patel ,  Ming Zeng ,  Tsung-Chuan Whang

IPC分类号： G01R31/317 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

CPC分类号： G01R31/31727 ,  H03K5/133 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03L7/0812

摘要： A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.

公开(公告)号：US06970029B2

公开(公告)日：2005-11-29

申请号：US10751135

申请日：2003-12-30

申请人： Bheem Patel ,  Ming Zeng ,  Tsung-Chuan Whang

发明人： Bheem Patel ,  Ming Zeng ,  Tsung-Chuan Whang

IPC分类号： G01R31/317 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

CPC分类号： G01R31/31727 ,  H03K5/133 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03L7/0812

摘要： A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.

摘要翻译： 可变延迟信号发生器电路包括延迟链和内插器电路。 延迟链产生多个多相信号，其中每个多相信号表示输入事件信号的延迟版本。 每个多相信号通过第一相位增量与连续信号分离。 内插器电路包括多个内插器块，其中每个块接收多相信号。 内插器电路在连续的内插器块之间内插，以产生表示输入事件信号的修改延迟版本的输出信号。 输出信号被延迟到存在于连续多相信号之间的多个相位延迟中的一个。 为了产生输出信号，基于电流源选择信号来调整每个内插器块内的可变电流源。 电流源选择信号由包括分流电源的偏置电路产生。