公开(公告)号：US20150311094A1

公开(公告)日：2015-10-29

申请号：US14794820

申请日：2015-07-09

申请人： Tsung Chuan Whang ,  Yi-Chieh Wang

发明人： Tsung Chuan Whang ,  Yi-Chieh Wang

IPC分类号： H01L21/48 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L21/4825 ,  H01L23/60 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0255 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85007 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/12036 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

摘要翻译： 公开了一种将多个集成电路管芯组装成系统级封装芯片的方法，该方法包括：提供多个集成电路管芯; 在所述多个集成电路管芯中的至少一个集成电路管芯上设置至少一个再分配层，用于在所述多个集成电路管芯之间进行导线连接，而不使用所述多个集成电路管芯下面的衬底; 在所述多个集成电路管芯之间建立电线连接并验证所述多个电线连接; 并将多个集成电路管芯和经验证的引线连接封装到系统级封装芯片中。

公开(公告)号：US09111846B1

公开(公告)日：2015-08-18

申请号：US14253868

申请日：2014-04-16

申请人： Tsung Chuan Whang ,  Yi-Chieh Wang

发明人： Tsung Chuan Whang ,  Yi-Chieh Wang

IPC分类号： H01L23/48 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/02

CPC分类号： H01L21/4825 ,  H01L23/60 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0255 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85007 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/12036 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： The present invention discloses an efficient way to connect multiple integrated circuit dies using redistribution layers (RDL) for making wire connections. Antenna diodes are used to create ground paths so as to remove non-sticking pads on the RDL to ensure the integrity of the wire connections before packaging the multiple integrated circuit dies into a system-in-package (SIP) chip, thereby eliminating unnecessary yield loss in a functional test caused by the non-sticking pads. In another aspect, electrostatic discharge (ESD) protection can be provided through the antenna diodes across two different power domains by disposing a diode in one integrated circuit die for ESD protection of a terminal in another integrated circuit die.

摘要翻译： 本发明公开了一种使用再分配层（RDL）连接多个集成电路管芯以实现线连接的有效方法。 天线二极管用于创建接地路径，以便在将多个集成电路管芯封装成系统级封装（SIP）芯片之前，去除RDL上的不粘焊盘以确保电线连接的完整性，从而消除不必要的产量 由不粘垫引起的功能测试中的损失。 另一方面，通过在一个集成电路管芯中设置二极管，在另一个集成电路管芯中的端子进行ESD保护，可以通过两个不同功率域上的天线二极管提供静电放电（ESD）保护。

公开(公告)号：US20050140417A1

公开(公告)日：2005-06-30

申请号：US10751135

申请日：2003-12-30

申请人： Bheem Patel ,  Ming Zeng ,  Tsung-Chuan Whang

发明人： Bheem Patel ,  Ming Zeng ,  Tsung-Chuan Whang

IPC分类号： G01R31/317 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

CPC分类号： G01R31/31727 ,  H03K5/133 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03L7/0812

摘要： A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.

公开(公告)号：US09349610B2

公开(公告)日：2016-05-24

申请号：US14794820

申请日：2015-07-09

申请人： Tsung Chuan Whang ,  Yi-Chieh Wang

发明人： Tsung Chuan Whang ,  Yi-Chieh Wang

IPC分类号： H01L21/48 ,  H01L25/18 ,  H01L25/00 ,  H01L27/02 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L21/4825 ,  H01L23/60 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0255 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85007 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/12036 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

摘要翻译： 公开了一种将多个集成电路管芯组装成系统级封装芯片的方法，该方法包括：提供多个集成电路管芯; 在所述多个集成电路管芯中的至少一个集成电路管芯上设置至少一个再分配层，用于在所述多个集成电路管芯之间进行导线连接，而不使用所述多个集成电路管芯下面的衬底; 在所述多个集成电路管芯之间建立电线连接并验证所述多个电线连接; 并将多个集成电路管芯和经验证的引线连接封装到系统级封装芯片中。

公开(公告)号：US06970029B2

公开(公告)日：2005-11-29

申请号：US10751135

申请日：2003-12-30

申请人： Bheem Patel ,  Ming Zeng ,  Tsung-Chuan Whang

发明人： Bheem Patel ,  Ming Zeng ,  Tsung-Chuan Whang

IPC分类号： G01R31/317 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

CPC分类号： G01R31/31727 ,  H03K5/133 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03L7/0812

摘要： A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.

摘要翻译： 可变延迟信号发生器电路包括延迟链和内插器电路。 延迟链产生多个多相信号，其中每个多相信号表示输入事件信号的延迟版本。 每个多相信号通过第一相位增量与连续信号分离。 内插器电路包括多个内插器块，其中每个块接收多相信号。 内插器电路在连续的内插器块之间内插，以产生表示输入事件信号的修改延迟版本的输出信号。 输出信号被延迟到存在于连续多相信号之间的多个相位延迟中的一个。 为了产生输出信号，基于电流源选择信号来调整每个内插器块内的可变电流源。 电流源选择信号由包括分流电源的偏置电路产生。

公开(公告)号：US5654665A

公开(公告)日：1997-08-05

申请号：US444111

申请日：1995-05-18

申请人： Suresh M. Menon ,  Tsung Chuan Whang

发明人： Suresh M. Menon ,  Tsung Chuan Whang

IPC分类号： G05F3/20 ,  G05F3/26 ,  G05F3/02

CPC分类号： G05F3/205 ,  G05F3/267

摘要： A biasing system for a differential amplifier includes an NMOS current source and a gate bias voltage generator. The gate bias voltage generator produces a bias voltage VNCS to control the NMOS current source. The gate bias generator includes a reference current generator to produce a reference current relatively independent of supply voltage variations. A temperature compensator regulates the reference current to provide a temperature compensated current. A current mirror duplicates the temperature compensated current to a bias voltage generator. The bias voltage generator generates the bias voltage.

摘要翻译： 用于差分放大器的偏置系统包括NMOS电流源和栅极偏置电压发生器。 栅极偏置电压发生器产生偏置电压VNCS以控制NMOS电流源。 栅极偏置发生器包括参考电流发生器，以产生相对独立于电源电压变化的参考电流。 温度补偿器调节参考电流以提供温度补偿电流。 电流镜将温度补偿电流复制到偏置电压发生器。 偏置电压发生器产生偏置电压。