公开(公告)号：US06346895B1

公开(公告)日：2002-02-12

申请号：US09769099

申请日：2001-01-24

申请人： Bhum-Cheol Lee ,  Jong-Moo Sohn ,  Eun-Chang Choi ,  Kwon-Chul Park

发明人： Bhum-Cheol Lee ,  Jong-Moo Sohn ,  Eun-Chang Choi ,  Kwon-Chul Park

IPC分类号： H03M500

CPC分类号： H03M5/00

摘要： A method for using a nibble(partial bits of word) inversion code in a network system includes the steps of: a) adding 1 redundancy bit to n bit source data and generating a pre-code, n being an even number of 2 or over; b) deciding the number of transitions in the generated pre-code; c) determining the pre-code as a code word if the number of transitions in the pre-code is greater than or equal to 1+n/2 in a deciding result; d) inverting alternate bits including the redundancy bit among bits constructing the pre-code and generating the code word, if the number of transitions in the pre-code is less than n/2 in the deciding result; e) determining the pre-code as the code word in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is not an in-band signaling and not a special word in the deciding result; and f) inverting the nibble among the bits constructing the pre-code and generating the code word, in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is an in-band signaling or is a special word in the deciding result.

摘要翻译： 一种在网络系统中使用半字节（部分位字）反转码的方法包括以下步骤：a）将1个冗余比特加到n比特源数据并产生一个预编码，n是2或更多的偶数 ; b）决定生成的代码中的转换次数; c）如果所述预代码中的转换次数在决定结果中大于或等于1 + n / 2，则将所述预代码确定为代码字; d）如果所述预代码中的转换次数小于所述判定结果中的n / 2，则将包括构成所述预代码的位中的所述冗余位的交替位反转并生成所述代码字; e）在预编码中的转换次数等于n / 2并且同时源数据不是带内信令而不是决定结果中的特殊字的情况下，将前缀代码确定为码字 ; 以及f）在构成前代码的比特中产生半字节并产生码字，在预编码中的转换次数等于n / 2的情况下，并且源数据是带内信令或 是决定结果中的一个特殊字。

公开(公告)号：US08050280B2

公开(公告)日：2011-11-01

申请号：US11292983

申请日：2005-12-01

申请人： Ick-Sung Choi ,  Jeong-Hee Lee ,  Dae-Geun Park ,  Hyoung-Il Lee ,  Jong-Moo Sohn ,  Seung-Woo Lee ,  Bhum-Cheol Lee

发明人： Ick-Sung Choi ,  Jeong-Hee Lee ,  Dae-Geun Park ,  Hyoung-Il Lee ,  Jong-Moo Sohn ,  Seung-Woo Lee ,  Bhum-Cheol Lee

IPC分类号： H04L12/56

CPC分类号： H04L49/3036 ,  H04L49/25 ,  H04L49/3072

摘要： An efficient switching device and a method for fabricating the same using multiple shared memories are provided. The switching device includes: an output time determination unit to determine an output time to an output port; an output time administration unit to administer a possible data output time for each output port; a memory bank selection unit to select a memory bank with an empty data output time position; a memory bank utilization information administration unit to administer utilization information per output time; a connection unit to deliver transmission data to an output time position; a shared memory unit to store the data in the output time position, to administer dispersed shared memory banks according to an output time, and to read and output transmission data; and an output port connection unit receiving output data to read and transmit output port information of the data to a corresponding output port.

摘要翻译： 提供了一种有效的开关器件及其使用多个共享存储器的制造方法。 开关装置包括：输出时间确定单元，用于确定到输出端口的输出时间; 输出时间管理单元，用于管理每个输出端口的可能的数据输出时间; 存储器选择单元，用于选择具有空数据输出时间位置的存储体; 存储库利用信息管理单元，用于管理每个输出时间的利用信息; 连接单元，用于将传输数据传送到输出时间位置; 共享存储器单元，用于将数据存储在输出时间位置，以根据输出时间来管理分散的共享存储体，并读取和输出传输数据; 以及输出端口连接单元，其接收输出数据以将数据的输出端口信息读取并发送到相应的输出端口。

公开(公告)号：US20060146851A1

公开(公告)日：2006-07-06

申请号：US11292983

申请日：2005-12-01

申请人： Ick-Sung Choi ,  Jeong-Hee Lee ,  Dae-Geun Park ,  Hyoung-Il Lee ,  Jong-Moo Sohn ,  Seung-Woo Lee ,  Bhum-Cheol Lee

发明人： Ick-Sung Choi ,  Jeong-Hee Lee ,  Dae-Geun Park ,  Hyoung-Il Lee ,  Jong-Moo Sohn ,  Seung-Woo Lee ,  Bhum-Cheol Lee

IPC分类号： H04L12/56 ,  H04L12/54

CPC分类号： H04L49/3036 ,  H04L49/25 ,  H04L49/3072

摘要： An efficient switching device and a method for fabricating the same using multiple shared memories are provided. The switching device includes: an output time determination unit to determine an output time to an output port; an output time administration unit to administer a possible data output time for each output port; a memory bank selection unit to select a memory bank with an empty data output time position; a memory bank utilization information administration unit to administer utilization information per output time; a connection unit to deliver transmission data to an output time position; a shared memory unit to store the data in the output time position, to administer dispersed shared memory banks according to an output time, and to read and output transmission data; and an output port connection unit receiving output data to read and transmit output port information of the data to a corresponding output port.

摘要翻译： 提供了一种有效的开关器件及其使用多个共享存储器的制造方法。 开关装置包括：输出时间确定单元，用于确定到输出端口的输出时间; 输出时间管理单元，用于管理每个输出端口的可能的数据输出时间; 存储器选择单元，用于选择具有空数据输出时间位置的存储体; 存储库利用信息管理单元，用于管理每个输出时间的利用信息; 连接单元，用于将传输数据传送到输出时间位置; 共享存储器单元，用于将数据存储在输出时间位置，以根据输出时间来管理分散的共享存储体，并读取和输出传输数据; 以及输出端口连接单元，其接收输出数据以将数据的输出端口信息读取并发送到相应的输出端口。

公开(公告)号：US5940018A

公开(公告)日：1999-08-17

申请号：US941214

申请日：1997-09-30

申请人： Jin-Young Kim ,  Bhum-Cheol Lee ,  Kwon-Chul Park

发明人： Jin-Young Kim ,  Bhum-Cheol Lee ,  Kwon-Chul Park

IPC分类号： H03M7/14 ,  H03M5/08 ,  H03M13/11 ,  H03M13/31 ,  H04B3/04 ,  H04L7/00 ,  H03M13/00

CPC分类号： H03M13/63 ,  H03M13/11 ,  H03M13/31 ,  H03M5/08

摘要： An nB2P coding/decoding device having a line code function facilitating data transmission and data recovery in the transmission line or link, and a function of a channel code for detecting errors in the recovered data, is provided, including: an nB2P coding device for dividing n bit width parallel data into two data units each having a predetermined bit width, and serial-transmitting the resulting n+2 bit coded data to which two odd parity bits are added, with predetermined n+2 bit with block synchronization data which is orthogonal to the coded data; and an nB2P decoding device for detecting the block synchronization data from the serially transmitted data, converts serial data to parallel form of n+2 bits, checking for errors in the coded data using the odd parity, and removing the odd parity to decode them into the original n bit width parallel data.

摘要翻译： 一种具有促进传输线或链路中的数据传输和数据恢复的线路代码功能的nB2P编码/解码装置，以及用于检测恢复数据中的错误的信道码的功能，包括：nB2P编码装置，用于分割 将n位宽的并行数据分割成具有预定位宽的两个数据单元，并且将具有两个奇校验位的所生成的n + 2位编码数据与预定的n + 2位串联发送，其中正交的块同步数据 到编码数据; 以及用于从串行发送数据检测块同步数据的nB2P解码装置，将串行数据转换成n + 2位的并行形式，使用奇校验检查编码数据中的错误，并且去除奇校验以将其解码为 原始n位宽的并行数据。

公开(公告)号：US5887040A

公开(公告)日：1999-03-23

申请号：US746992

申请日：1996-11-19

申请人： Hee-Young Jung ,  Bhum-Cheol Lee ,  Kwon-Chul Park

发明人： Hee-Young Jung ,  Bhum-Cheol Lee ,  Kwon-Chul Park

IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04

CPC分类号： H04L7/0338

摘要： The present invention provides a high speed digital data retiming apparatus, in which, in binary data bits transmitted at a high speed, the data can be retimed in a stable manner, even if there are present a static skew due to a delay difference between the retiming clock pulse and the data and a dynamic skew due to the characteristic variation according to time and temperature. Therefore, the present invention has the following advantages compared with the conventional apparatus. First, periodical and regular external clock pulses are delayed by means of a delaying section, so that system performance is independent of the pattern of data. Second, even if the data phases show a continuous difference (wandering) for more than a certain period of time, an elastic buffer absorbs the wandering, and therefore, no data loss is generated, with the result that the system is not put to a disorder condition. Third, even in the case where a metastable state occurs, its occurrence probability can be significantly reduced by utilizing logic, thereby making it possible to retime the data in stable manner.

摘要翻译： 本发明提供了一种高速数字数据重定时装置，其中，在以高速发送的二进制数据位中，即使存在静态偏移，也可以以稳定的方式重新定时， 重新定时钟脉冲和数据以及由于根据时间和温度的特性变化而产生的动态偏移。 因此，与现有技术相比，本发明具有以下优点。 首先，周期性和规则的外部时钟脉冲通过延迟部分被延迟，使得系统性能与数据模式无关。 第二，即使数据相位显示出持续的差异（漫游）一段时间，弹性缓冲器也可以吸收漂移，因此不会产生数据丢失，结果系统不会 无序状态。 第三，即使在发生亚稳态的情况下，也可以通过利用逻辑来显着降低其发生概率，从而使得可以以稳定的方式重新计算数据。

公开(公告)号：US20110051730A1

公开(公告)日：2011-03-03

申请号：US12845335

申请日：2010-07-28

申请人： Dong-Myoung BAEK ,  Bhum-Cheol Lee ,  Jung-Hee Lee ,  Sang-Yoon Oh ,  Seung-Woo Lee

发明人： Dong-Myoung BAEK ,  Bhum-Cheol Lee ,  Jung-Hee Lee ,  Sang-Yoon Oh ,  Seung-Woo Lee

IPC分类号： H04L12/56

CPC分类号： H04W80/00 ,  H04L69/08 ,  H04L69/32

摘要： A multi-layer data processing apparatus and method. The multi-layer data processing unit may classify received multi-layer data into lower layer data and higher layer data using lower layer information, and generate and output a traffic flow of the lower layer data or traffic flows of the lower layer data and the higher layer data with reference to a rule information table. In the rule information table, pieces of lower layer rule information may be linked to pieces of higher layer rule information.

摘要翻译： 一种多层数据处理装置和方法。 多层数据处理单元可以使用较低层信息将接收的多层数据分类为较低层数据和较高层数据，并生成并输出较低层数据的业务流或较低层数据的业务流和较高层数据 参考规则信息表的层数据。 在规则信息表中，下层规则信息可以链接到多条高层规则信息。

公开(公告)号：US08934506B2

公开(公告)日：2015-01-13

申请号：US13328269

申请日：2011-12-16

申请人： Seung-Woo Lee ,  Bhum-Cheol Lee ,  Jung-Hee Lee

发明人： Seung-Woo Lee ,  Bhum-Cheol Lee ,  Jung-Hee Lee

IPC分类号： H04J3/06

CPC分类号： H04J3/0697 ,  H04J3/0638 ,  H04J3/0658 ,  H04J3/0667

摘要： An apparatus includes a difference extraction unit to extract a difference between a second time stamp value, which is obtained by adjusting a first time stamp value that is measured at a time of arrival of a synchronization message transmitted by the master at a Layer 3 to be synchronized in frequency with a clock of the master, and a third time stamp value, which is measured at a time of departure of the synchronization message from the master; a minimum filter to select a minimum from one or more difference values extracted by the difference extraction unit; and a delay variation calculation unit to estimate a time of arrival of a current synchronization message at the Layer 3 based on the selected minimum and calculate a delay variation.

摘要翻译： 一种装置，包括差分提取单元，用于提取第二时间标记值之间的差异，该第二时间戳值是通过调整由第三层发送的由主机发送的同步消息的到达时所测量的第一时间戳值而获得的 频率与主机的时钟同步，以及第三时间戳值，其在与主机的同步消息的离开时测量; 最小滤波器，用于从由所述差分提取单元提取的一个或多个差值中选择最小值; 以及延迟变化计算单元，基于所选择的最小值来估计当前同步消息在层3的到达时间，并计算延迟变化。

公开(公告)号：US20060126622A1

公开(公告)日：2006-06-15

申请号：US11302604

申请日：2005-12-13

申请人： Dae-Geun Park ,  Bhum-Cheol Lee

发明人： Dae-Geun Park ,  Bhum-Cheol Lee

IPC分类号： H04L12/56

CPC分类号： H04L29/12009 ,  H04L29/12584 ,  H04L29/12839 ,  H04L61/2596 ,  H04L61/6022

摘要： Provided is an apparatus for changing Media Access Control (MAC) address, which is a conventional subscriber hardware identification address for identifying each subscriber, and a method thereof. The MAC address changing apparatus includes a frame receiving block for determining whether to change a source MAC address; a switch controlling block for controlling a switch; a change MAC address generating block for changing the source MAC address of the received frame; a change MAC address storing block for storing information of the change MAC address and the source MAC address corresponding thereto; a MAC address forwarding and lookup block for extracting output port information; a MAC address replacing block for forming an output frame by replacing the source MAC address; a MAC address storing block for storing a MAC address; and a frame transmitting block for transmitting the output frame.

摘要翻译： 提供了一种用于改变媒体访问控制（MAC）地址的装置，其是用于识别每个订户的常规用户硬件标识地址及其方法。 MAC地址改变装置包括用于确定是否改变源MAC地址的帧接收块; 用于控制开关的开关控制块; 改变MAC地址生成块，用于改变接收到的帧的源MAC地址; 更改MAC地址存储块，用于存储与其对应的改变MAC地址和源MAC地址的信息; 用于提取输出端口信息的MAC地址转发和查找块; 用于通过替换源MAC地址来形成输出帧的MAC地址替换块; 用于存储MAC地址的MAC地址存储块; 以及用于发送输出帧的帧发送块。

公开(公告)号：US07990966B2

公开(公告)日：2011-08-02

申请号：US11302604

申请日：2005-12-13

申请人： Dae-Geun Park ,  Bhum-Cheol Lee

发明人： Dae-Geun Park ,  Bhum-Cheol Lee

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04J3/24 ,  G06F15/173

CPC分类号： H04L29/12009 ,  H04L29/12584 ,  H04L29/12839 ,  H04L61/2596 ,  H04L61/6022

摘要： Provided is an apparatus for changing Media Access Control (MAC) address, which is a conventional subscriber hardware identification address for identifying each subscriber, and a method thereof. The MAC address changing apparatus includes a frame receiving block for determining whether to change a source MAC address; a switch controlling block for controlling a switch; a change MAC address generating block for changing the source MAC address of the received frame; a change MAC address storing block for storing information of the change MAC address and the source MAC address corresponding thereto; a MAC address forwarding and lookup block for extracting output port information; a MAC address replacing block for forming an output frame by replacing the source MAC address; a MAC address storing block for storing a MAC address; and a frame transmitting block for transmitting the output frame.

摘要翻译： 提供了一种用于改变媒体访问控制（MAC）地址的装置，其是用于识别每个订户的常规用户硬件标识地址及其方法。 MAC地址改变装置包括：用于确定是否改变源MAC地址的帧接收块; 用于控制开关的开关控制块; 改变MAC地址生成块，用于改变接收到的帧的源MAC地址; 更改MAC地址存储块，用于存储与其对应的改变MAC地址和源MAC地址的信息; 用于提取输出端口信息的MAC地址转发和查找块; 用于通过替换源MAC地址来形成输出帧的MAC地址替换块; 用于存储MAC地址的MAC地址存储块; 以及用于发送输出帧的帧发送块。

公开(公告)号：US06904047B2

公开(公告)日：2005-06-07

申请号：US09860273

申请日：2001-05-17

申请人： Man-Soo Han ,  Jung-Hee Lee ,  In-Tack Han ,  Bhum-Cheol Lee

发明人： Man-Soo Han ,  Jung-Hee Lee ,  In-Tack Han ,  Bhum-Cheol Lee

IPC分类号： H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04L12/56

CPC分类号： H04L49/1576 ,  H04L49/1523 ,  H04L49/3018 ,  H04L49/3027 ,  H04L2012/5679 ,  H04L2012/5683

摘要： A method for scheduling an input and output buffered ATM or packet switch and, more particularly, to a method for cell-scheduling an input and output buffered switch that is adapted to a high-speed large switch is provided. The input and output buffered switch has multiple switching planes, and its structure is used to compensated for decreasing performance of the input buffered switch resulting from HOL (head-of-line) blocking of the input buffered switch. The input and output buffered switch consists of input buffer modules grouping several input ports and output ports and output buffer modules, and each input buffer module has several FIFO queues for the associated module output buffer modules. In the input and output buffered switch having multiple switching planes, cell scheduling is carried out using a simple iterative matching (SIM) method. The SIM method consists of three operations, those are, request operation, grant operation, and accepting operation, and in the SIM method, the operations are iteratively carried out several times in one cell period, thereby matching efficiency can be increased. Each input buffered module determines simultaneously multiple FIFO queues served in one cell period, so that the SIM method with multiple selection ability has higher speed operations and better performance than conventional scheduling methods.

摘要翻译： 提供一种用于调度输入和输出缓冲的ATM或分组交换机的方法，更具体地说，涉及一种适用于高速大型交换机的输入和输出缓冲交换机的小区调度方法。 输入和输出缓冲开关具有多个开关平面，其结构用于补偿由输入缓冲开关的HOL（线头）阻塞导致的输入缓冲开关的性能下降。 输入和输出缓冲交换机由输入缓冲区模块组成，分组几个输入端口和输出端口以及输出缓冲模块，每个输入缓冲区模块都有相应的模块输出缓冲模块的多个FIFO队列。 在具有多个交换平面的输入和输出缓冲交换机中，使用简单的迭代匹配（SIM）方法进行小区调度。 SIM方法由三种操作，即请求操作，授权操作和接受操作三种操作，在SIM方法中，在一个单元周期内对该操作进行多次迭代，可以提高匹配效率。 每个输入缓冲模块同时确定在一个单元周期内服务的多个FIFO队列，使得具有多种选择能力的SIM方法具有比传统调度方法更高的速度操作和更好的性能。