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公开(公告)号：US09916213B1
公开(公告)日：2018-03-13
申请号：US14688209
申请日：2015-04-16
Applicant: BiTMICRO Networks, Inc.
CPC classification number: G06F11/2007 , G06F11/2002 , G06F11/2005 , G06F11/2017 , G06F11/202 , G06F11/2023 , G06F11/2041 , G06F13/1605 , G06F13/366 , G06F13/4031
Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
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公开(公告)号：US10430303B1
公开(公告)日：2019-10-01
申请号：US15891147
申请日：2018-02-07
Applicant: BITMICRO Networks, Inc.
Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
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公开(公告)号：US10423554B1
公开(公告)日：2019-09-24
申请号：US15790299
申请日：2017-10-23
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Cyrill Coronel Ponce , Jarmie Dela Cruz Espuerta
IPC: G06F13/20 , G06F13/366 , G06F13/00
Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.
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公开(公告)号：US09798688B1
公开(公告)日：2017-10-24
申请号：US14216627
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Cyrill Coronel Ponce , Jarmie Dela Cruz Espuerta
IPC: G06F13/20 , G06F13/366 , G06F13/00
CPC classification number: G06F13/366
Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.
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