公开(公告)号：US06708248B1

公开(公告)日：2004-03-16

申请号：US09457155

申请日：1999-12-08

申请人： Billy Wayne Garrett, Jr. ,  Frederick Abbott Ware ,  Craig E. Hampel ,  Richard M. Barth ,  Donald C. Stark ,  Abhijit Mukund Abhyankar ,  Catherine Yuhjung Chen ,  Thomas J. Sheffler ,  Ely K. Tsern ,  Steven Cameron Woo

发明人： Billy Wayne Garrett, Jr. ,  Frederick Abbott Ware ,  Craig E. Hampel ,  Richard M. Barth ,  Donald C. Stark ,  Abhijit Mukund Abhyankar ,  Catherine Yuhjung Chen ,  Thomas J. Sheffler ,  Ely K. Tsern ,  Steven Cameron Woo

IPC分类号： G06F1200

CPC分类号： G06F13/1657 ,  G06F13/1684 ,  Y02D10/14

摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

公开(公告)号：US07039782B2

公开(公告)日：2006-05-02

申请号：US10690402

申请日：2003-10-20

申请人： Billy Wayne Garrett, Jr. ,  Frederick Abbott Ware ,  Craig E. Hampel ,  Richard M. Barth ,  Donald C. Stark ,  Abhijit Mukund Abhyankar ,  Catherine Yuhjung Chen ,  Thomas J. Sheffler ,  Ely K. Tsern ,  Steven Cameron Woo

发明人： Billy Wayne Garrett, Jr. ,  Frederick Abbott Ware ,  Craig E. Hampel ,  Richard M. Barth ,  Donald C. Stark ,  Abhijit Mukund Abhyankar ,  Catherine Yuhjung Chen ,  Thomas J. Sheffler ,  Ely K. Tsern ,  Steven Cameron Woo

IPC分类号： G06F12/00

CPC分类号： G06F13/1657 ,  G06F13/1684 ,  Y02D10/14

摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

摘要翻译： 公开了一种高速存储器系统，其中单个命令根据当前的操作模式对单个存储器件或多个存储器件进行控制。 这种控制可以影响一个或多个存储器件与存储器控制器之间的数据传输，以及存储器件的操作状态转换或功率模式转换。 类似地，相对低带宽的存储器件的各种配置作为有选择地控制的组进行响应以发送或接收高带宽数据。

公开(公告)号：US06370668B1

公开(公告)日：2002-04-09

申请号：US09395160

申请日：1999-09-14

申请人： Billy Wayne Garrett, Jr. ,  Frederick Abbott Ware ,  Craig E. Hampel ,  Richard M. Barth ,  Don Stark ,  Abhijit Mukund Abhyankar ,  Catherine Yuhjung Chen ,  Thomas J. Sheffler ,  Ely K. Tsern ,  Steven Cameron Woo

发明人： Billy Wayne Garrett, Jr. ,  Frederick Abbott Ware ,  Craig E. Hampel ,  Richard M. Barth ,  Don Stark ,  Abhijit Mukund Abhyankar ,  Catherine Yuhjung Chen ,  Thomas J. Sheffler ,  Ely K. Tsern ,  Steven Cameron Woo

IPC分类号： G11C2900

CPC分类号： G06F11/1028 ,  G06F11/1044 ,  G11C7/1072

摘要： The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.

摘要翻译： 本发明提供能够以非芯片杀死和芯片杀死模式操作的高数据带宽存储系统。 在芯片杀死模式中，循环复用，位复用和时间和空间复用用于跨一组存储器件读/写数据和校正。 当前命令分组格式适于以芯片杀死模式与该组存储器件进行通信。

公开(公告)号：US06839266B1

公开(公告)日：2005-01-04

申请号：US10101243

申请日：2002-03-20

申请人： Billy Wayne Garrett, Jr. ,  Frederick Abbott Ware ,  Craig E. Hampel ,  Richard M. Barth ,  Don Stark ,  Abhijit Mukund Abhyankar ,  Catherine Yuhjung Chen ,  Thomas J. Sheffler ,  Ely K. Tsern ,  Steven Cameron Woo

发明人： Billy Wayne Garrett, Jr. ,  Frederick Abbott Ware ,  Craig E. Hampel ,  Richard M. Barth ,  Don Stark ,  Abhijit Mukund Abhyankar ,  Catherine Yuhjung Chen ,  Thomas J. Sheffler ,  Ely K. Tsern ,  Steven Cameron Woo

IPC分类号： G06F11/10 ,  G11C7/10 ,  G11C29/00 ,  G06F13/40

CPC分类号： G06F11/1028 ,  G06F11/1044 ,  G11C7/1072

摘要： A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

公开(公告)号：US06704891B2

公开(公告)日：2004-03-09

申请号：US10453368

申请日：2003-06-02

申请人： Steven Cameron Woo ,  John Philip Privitera ,  Mark Alan Horowitz

发明人： Steven Cameron Woo ,  John Philip Privitera ,  Mark Alan Horowitz

IPC分类号： G11C2900

CPC分类号： G11C29/56004 ,  G11C29/54 ,  G11C29/56012

摘要： A method of generating and verifying a memory test is disclosed. A simulator is used to verify that the sequence of time-ordered commands complies with a set of operating constraints for the memory. A packer may thereafter be used to optimize run time of the verified test.

摘要翻译： 公开了一种生成和验证存储器测试的方法。 模拟器用于验证时序命令的顺序符合存储器的一组操作约束。 此后可以使用封隔器来优化验证测试的运行时间。

公开(公告)号：US06574759B1

公开(公告)日：2003-06-03

申请号：US09484431

申请日：2000-01-18

申请人： Steven Cameron Woo ,  John Philip Privitera ,  Mark Alan Horowitz

发明人： Steven Cameron Woo ,  John Philip Privitera ,  Mark Alan Horowitz

IPC分类号： G11C2900

CPC分类号： G11C29/56004 ,  G11C29/54 ,  G11C29/56012

摘要： A method of generating and verifying a memory test is disclosed. A simulator is used to verify that the sequence of time-ordered commands complies with a set of operating constraints for the memory. A packer may thereafter be used to optimize run time of the verified test.

摘要翻译： 公开了一种生成和验证存储器测试的方法。 模拟器用于验证时序命令的顺序符合存储器的一组操作约束。 此后可以使用封隔器来优化验证测试的运行时间。