公开(公告)号：US08680624B2

公开(公告)日：2014-03-25

申请号：US13488109

申请日：2012-06-04

Applicant: Man Fai Ng ,  Bin Yang

Inventor： Man Fai Ng ,  Bin Yang

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/76267 ,  H01L21/823878 ,  H01L29/66772

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract translation: 提供了用于制造在绝缘材料区域内具有阻挡区域的半导体器件的方法和装置，导致从绝缘材料区域的脱气路径。 一种方法包括在靠近半导体材料的隔离区域的绝缘材料内形成阻挡区域，并形成覆盖半导体材料的隔离区域的栅极结构。 阻挡区域与半导体材料的隔离区域相邻，导致绝缘材料内的除气路径。

公开(公告)号：US08394691B2

公开(公告)日：2013-03-12

申请号：US12814346

申请日：2010-06-11

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L21/8238

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.

Abstract translation: 提供了半导体器件结构和相关制造方法的装置。 制造半导体器件结构的一种方法包括形成覆盖半导体材料区域的栅极结构，其中栅极结构的宽度与半导体材料的<100>晶体方向对齐。 该方法通过在栅极结构周围形成凹槽并在凹部中形成应力诱导半导体材料来继续。

公开(公告)号：US08518758B2

公开(公告)日：2013-08-27

申请号：US12726889

申请日：2010-03-18

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L27/12

CPC classification number: H01L29/78618 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

Abstract translation: 在诸如极薄的SOI（ETSOI）衬底的SOI衬底上形成半导体，具有增加的延伸厚度。 实施例包括在SOI衬底上具有外延形成的含硅层（例如嵌入硅锗（eSiGe））的半导体器件。 实施例包括形成SOI衬底，在SOI衬底上外延形成含硅层，并在外延形成的含硅层上形成栅电极。 在形成栅极间隔物和源极/漏极区之后，去除栅电极和下面的含硅层，并用高k金属栅极代替。 使用外延形成的含硅层由于制造工艺侵蚀而减少SOI厚度损失，从而增加延伸厚度并降低延伸电阻。

公开(公告)号：US08198170B2

公开(公告)日：2012-06-12

申请号：US12905805

申请日：2010-10-15

Applicant: Man Fai Ng ,  Bin Yang

Inventor： Man Fai Ng ,  Bin Yang

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.

Abstract translation: 提供了半导体器件结构的制造方法。 该器件结构具有一层硅层和一层覆盖硅层的二氧化硅层，该方法开始于通过去除一部分二氧化硅和一部分硅来形成隔离凹槽。 隔离凹部填充有应力诱导性氮化硅，然后去除二氧化硅，使得应力诱导性氮化硅突出于硅上方。 接下来，暴露的硅被热氧化以形成覆盖在硅上的二氧化硅硬掩模材料。 此后，去除二氧化硅硬掩模材料的第一部分以露出硅的可接近表面，同时留下二氧化硅硬掩模材料的第二部分完好无损。 接下来，从硅的可接近表面外延生长硅锗。

公开(公告)号：US20110241118A1

公开(公告)日：2011-10-06

申请号：US12750340

申请日：2010-03-30

Applicant: Man Fai Ng ,  Bin Yang

Inventor： Man Fai Ng ,  Bin Yang

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.

Abstract translation: 形成具有减小的栅极空隙的高k金属栅电极。 一个实施例包括形成可替换的栅电极，例如具有顶表面和底表面的非晶硅，顶表面大于底表面，去除可更换的栅电极，形成具有大于 底部开口，并用金属填充空腔。 可以通过在比顶部更高的温度下蚀刻非晶硅的底部，或者通过不同地掺杂非晶硅的顶部和底部来形成较大的顶表面，使得底部具有比顶部更大的侧向蚀刻速率 。

公开(公告)号：US08987110B2

公开(公告)日：2015-03-24

申请号：US13467730

申请日：2012-05-09

Applicant: Man Fai Ng ,  Bin Yang

Inventor： Man Fai Ng ,  Bin Yang

IPC: H01L21/762 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.

Abstract translation: 提供了半导体器件结构的制造方法。 器件结构具有硅层和覆盖硅层的二氧化硅层，并且该方法开始于通过去除一部分二氧化硅和一部分硅来形成隔离凹槽。 隔离凹部填充有应力诱导性氮化硅，然后去除二氧化硅，使得应力诱导性氮化硅突出于硅上方。 接下来，暴露的硅被热氧化以形成覆盖在硅上的二氧化硅硬掩模材料。 此后，去除二氧化硅硬掩模材料的第一部分以露出硅的可接近表面，同时留下二氧化硅硬掩模材料的第二部分完好无损。 接下来，从硅的可接近表面外延生长硅锗。

公开(公告)号：US08765537B2

公开(公告)日：2014-07-01

申请号：US13606035

申请日：2012-09-07

Applicant: Man Fai Ng ,  Bin Yang

Inventor： Man Fai Ng ,  Bin Yang

IPC: H01L21/338

CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.

Abstract translation: 形成具有减小的栅极空隙的高k金属栅电极。 一个实施例包括形成可替换的栅电极，例如具有顶表面和底表面的非晶硅，顶表面大于底表面，去除可更换的栅电极，形成具有大于 底部开口，并用金属填充空腔。 可以通过在比顶部更高的温度下蚀刻非晶硅的底部，或者通过不同地掺杂非晶硅的顶部和底部来形成较大的顶表面，使得底部具有比顶部更大的侧向蚀刻速率 。

公开(公告)号：US20110227157A1

公开(公告)日：2011-09-22

申请号：US12726889

申请日：2010-03-18

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/78618 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

Abstract translation: 在诸如极薄的SOI（ETSOI）衬底的SOI衬底上形成半导体，具有增加的延伸厚度。 实施例包括在SOI衬底上具有外延形成的含硅层（例如嵌入硅锗（eSiGe））的半导体器件。 实施例包括形成SOI衬底，在SOI衬底上外延形成含硅层，并在外延形成的含硅层上形成栅电极。 在形成栅极间隔物和源极/漏极区之后，去除栅电极和下面的含硅层，并用高k金属栅极代替。 使用外延形成的含硅层由于制造工艺侵蚀而减少SOI厚度损失，从而增加延伸厚度并降低延伸电阻。

公开(公告)号：US08445342B2

公开(公告)日：2013-05-21

申请号：US12821507

申请日：2010-06-23

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L21/338

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833

Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

Abstract translation: 短沟道半导体器件形成有与栅电极的底部彼此分离的晕圈。 实施例包括在形成源极/漏极区域和源极/漏极延伸区域之后注入晕圈。 一个实施例包括在衬底中形成源极/漏极延伸区域，在衬底中形成源极/漏极区域，在形成源极漏极区域之后在源极/漏极延伸区域下方形成卤素区域，以及在衬底上形成栅极电极 源/漏区。 通过在涉及源极/漏极和源极/漏极延伸区域的高温处理之后形成晕圈区域，使得光晕扩散最小化，从而在晕圈区域之间保持足够的距离并且减少短沟道NMOS Vt滚降。

公开(公告)号：US20130005128A1

公开(公告)日：2013-01-03

申请号：US13606035

申请日：2012-09-07

Applicant: Man Fai NG ,  Bin Yang

Inventor： Man Fai NG ,  Bin Yang

IPC: H01L21/283

CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.

Abstract translation: 形成具有减小的栅极空隙的高k金属栅电极。 一个实施例包括形成可替换的栅电极，例如具有顶表面和底表面的非晶硅，顶表面大于底表面，去除可更换的栅电极，形成具有大于 底部开口，并用金属填充空腔。 可以通过在比顶部更高的温度下蚀刻非晶硅的底部，或者通过不同地掺杂非晶硅的顶部和底部来形成较大的顶表面，使得底部具有比顶部更大的横向蚀刻速率 。