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1.发明申请公开(公告)号：US20070079149A1
公开(公告)日：2007-04-05
申请号：US11241277
申请日：2005-09-30
IPC分类号： G06F1/26
CPC分类号： H03K3/0375 , H03K3/356147 , H03K19/0008
摘要： The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
摘要翻译： 本发明包括一个微控制器单元，其包括用于产生掉电信号的处理器。 控制逻辑响应于掉电信号产生保持信号。 电压调节器响应于输入电压提供调节电压，并响应于掉电信号而断电。 响应于稳压器进入断电状态，由调节电压供电的至少一个数字设备进入断电模式。 所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。 输入/输出单元也被连接以接收保持信号。 当至少一个数字设备进入掉电状态时，输入/输出单元响应于保持信号维持数字输出信号的最后状态。
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公开(公告)号：US20070079148A1
公开(公告)日：2007-04-05
申请号：US11240923
申请日：2005-09-30
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , H03K19/0016
摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.
摘要翻译： 微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。 响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。 电压调节器从输入电压产生调节电压。 电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。
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公开(公告)号：US07502434B2
公开(公告)日：2009-03-10
申请号：US10813243
申请日：2004-03-30
申请人： Eric T. King , Douglas Pastorello
发明人： Eric T. King , Douglas Pastorello
CPC分类号： H04L7/0337 , H03L7/113
摘要： A frequency detector and frequency-locked loop suitable for use in a clock recovery circuit are disclosed. The detector is linear, and can be used in implementing a loss of lock indicator. Variable delay filtering permits the frequency detector to be less sensitive to data fluctuations, and random or pseudo random addition of jitter helps address low gain in the data stream. A VCO controller cycles through a number of control states and provides varying levels of gain, dither and delay during each of the control states.
摘要翻译： 公开了一种适用于时钟恢复电路的频率检测器和频率锁相环。 检测器是线性的，可用于实现锁定指示器的丢失。 可变延迟滤波允许频率检测器对数据波动较不敏感，并且抖动的随机或伪随机添加有助于解决数据流中的低增益。 VCO控制器循环多个控制状态，并在每个控制状态期间提供不同程度的增益，抖动和延迟。
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公开(公告)号：US20070139088A1
公开(公告)日：2007-06-21
申请号：US11680026
申请日：2007-02-28
申请人： Akhil Garlapati , Lizhong Sun , Douglas Pastorello , Richard Juhn , Axel Thomsen
发明人： Akhil Garlapati , Lizhong Sun , Douglas Pastorello , Richard Juhn , Axel Thomsen
IPC分类号： H03K23/00
CPC分类号： H03K23/66 , H03K21/10 , H03L7/0805 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/193 , H03L7/1974 , H03L7/1976
摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.
摘要翻译： 在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号 。 第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。 至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。 该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。
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公开(公告)号：US20050242848A1
公开(公告)日：2005-11-03
申请号：US10878198
申请日：2004-06-28
申请人： Lizhong Sun , Douglas Pastorello , Richard Juhn , Axel Thomsen
发明人： Lizhong Sun , Douglas Pastorello , Richard Juhn , Axel Thomsen
CPC分类号： H03K23/66 , H03L7/193 , H03L7/1976
摘要： A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.
摘要翻译： 相位选择分频电路包括接收具有共同频率和不同相位的多个信号的选择电路。 选择具有第一相位的多个信号中的一个作为选择器电路输出信号。 对应于第一相位的第一值与对应于从第一相位的相位偏移的第二值相加，以产生指示其的和。 该和用于选择具有第二相位的第二信号作为下一个选择器电路输出信号。 当产生连续的和时，由选择器电路提供具有期望频率的脉冲串。
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公开(公告)号：US20050220233A1
公开(公告)日：2005-10-06
申请号：US10813243
申请日：2004-03-30
申请人： Eric King , Douglas Pastorello
发明人： Eric King , Douglas Pastorello
CPC分类号： H04L7/0337 , H03L7/113
摘要： A frequency detector and frequency-locked loop suitable for use in a clock recovery circuit are disclosed. The detector is linear, and can be used in implementing a loss of lock indicator. Variable delay filtering permits the frequency detector to be less sensitive to data fluctuations, and random or pseudo random addition of jitter helps address low gain in the data stream. A VCO controller cycles through a number of control states and provides varying levels of gain, dither and delay during each of the control states.
摘要翻译： 公开了一种适用于时钟恢复电路的频率检测器和频率锁相环。 检测器是线性的，可用于实现锁定指示器的丢失。 可变延迟滤波允许频率检测器对数据波动较不敏感，并且抖动的随机或伪随机添加有助于解决数据流中的低增益。 VCO控制器循环多个控制状态，并在每个控制状态期间提供不同程度的增益，抖动和延迟。
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公开(公告)号：US20050212570A1
公开(公告)日：2005-09-29
申请号：US10807852
申请日：2004-03-24
申请人： Lizhong Sun , Bruce Signore , Axel Thomsen , Douglas Pastorello
发明人： Lizhong Sun , Bruce Signore , Axel Thomsen , Douglas Pastorello
CPC分类号： H03K21/40 , H03K21/08 , H03K23/667
摘要： A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.
摘要翻译： 本文公开了一种分频器。 分频器包括可编程地耦合以提供各种分频比的分频级序列。 分频器还包括一个或多个多路复用器，用于将分频级的输出反馈到除法级序列之前的分频级的输入端。 分频器还可以包括占空比校正电路和用于校正异常逻辑状态的自校正逻辑。 分级阶段可以相互同步运行。 多路复用器功能，自校正电路功能和分频功能可以在组合锁存电路中实现。
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