公开(公告)号：US20060168393A1

公开(公告)日：2006-07-27

申请号：US11044567

申请日：2005-01-27

申请人： Bjorn Christensen ,  Peter Klim ,  Dung Nguyen ,  Raymond Yeung

发明人： Bjorn Christensen ,  Peter Klim ,  Dung Nguyen ,  Raymond Yeung

IPC分类号： G06F12/14

CPC分类号： G06F9/30141 ,  G06F9/30134 ,  G06F9/3828 ,  G06F9/3838 ,  G06F9/3867

摘要： An apparatus and method for dependency tracking and register file bypass controls using a scannable register file are provided. With the apparatus and method, a scannable register file array is provided and used to track the stage of any instruction in the execution unit. Every entry in the target vector is updated every cycle to stay synchronized with the instructions in the execution unit. To keep the register file array synchronized with the instructions in the execution unit, a right shift of all the data in each entry of the register file array occurs every cycle. The scan port of the register file array cells is used as the shift function.

摘要翻译： 提供了使用可扫描寄存器文件的依赖关系跟踪和寄存器文件旁路控制的装置和方法。 利用该装置和方法，提供可扫描的寄存器文件阵列并用于跟踪执行单元中任何指令的阶段。 每个周期更新目标向量中的每个条目，以与执行单元中的指令保持同步。 为了使寄存器文件阵列与执行单元中的指令保持同步，每个周期都会发生寄存器文件阵列的每个条目中所有数据的右移。 寄存器文件阵列单元的扫描端口用作移位功能。

公开(公告)号：US20050099851A1

公开(公告)日：2005-05-12

申请号：US10703017

申请日：2003-11-06

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： G11C7/10 ,  G11C8/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1012 ,  G11C7/1051 ,  G11C8/10

摘要： A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.

摘要翻译： 位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。 各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。 选择器处于耦合到相应输出节点的Q组中。 每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。 第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。 第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。 用于N + 1个多路复用器的输出逻辑门分别​​具有分别耦合到R个节点的R个输入。 多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。

公开(公告)号：US20080013395A1

公开(公告)日：2008-01-17

申请号：US11780038

申请日：2007-07-19

申请人： Zhibin Cheng ,  Satyajit Dutta ,  Peter Klim

发明人： Zhibin Cheng ,  Satyajit Dutta ,  Peter Klim

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/148

摘要： A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

摘要翻译： 本地动态功率控制器（LDPC）产生负载全摆幅电压信号和降低的摆幅电压电源信号。 全电源和降压电源都是从单个电源产生的。 当负载处于完全工作模式时，提供全摆幅电压供应信号，而当负载处于睡眠模式时提供降压电压信号。 因此，减少了在负载中消耗的功率。

公开(公告)号：US20070257731A1

公开(公告)日：2007-11-08

申请号：US11779991

申请日：2007-07-19

申请人： Zhibin Cheng ,  Satyajit Dutta ,  Peter Klim

发明人： Zhibin Cheng ,  Satyajit Dutta ,  Peter Klim

IPC分类号： G05F3/02

CPC分类号： G11C5/147 ,  G11C5/148

摘要： A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

摘要翻译： 本地动态功率控制器（LDPC）产生负载全摆幅电压信号和降低的摆幅电压电源信号。 全电源和降压电源都是从单个电源产生的。 当负载处于完全工作模式时，提供全摆幅电压供应信号，而当负载处于睡眠模式时提供降压电压信号。 因此，减少了在负载中消耗的功率。

公开(公告)号：US20070171757A1

公开(公告)日：2007-07-26

申请号：US11340535

申请日：2006-01-26

申请人： Michael Lee ,  Jose Paredes ,  Peter Klim ,  Sam Chu

发明人： Michael Lee ,  Jose Paredes ,  Peter Klim ,  Sam Chu

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

摘要翻译： 一种基于写入数据的选择性行激励的系统和方法，具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联，并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及M位行驱动器装置116，响应于M行104中的每一个的均匀字数据位，以禁止均匀字数据位为第一值的M行104的通电。

公开(公告)号：US20060038588A1

公开(公告)日：2006-02-23

申请号：US10922271

申请日：2004-08-19

申请人： Sam Chu ,  Peter Klim ,  Michael Hyeok Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Hyeok Lee ,  Jose Paredes

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation provides a compact circuit for blocking the indication of a non-evaluated state of a dynamic logic gate until a control signal has ended. The control signal is connected to a precharge input of the control element and a summing node is connected to one or more evaluation trees and to the control element output via an inverter. The inverter is connected to an override circuit that forces the output of the control element to a state opposite the precharge state until the control signal has ended. The output of the control element then assumes a state corresponding to the precharge state until an evaluation occurs. The control element output thus produces a window signal indicating the interval between the end of the control signal and the evaluation.

摘要翻译： 用于发信号通知控制信号的结束与逻辑评估之间的间隔的动态静态逻辑控制元件提供紧凑的电路，用于阻止动态逻辑门的未评估状态的指示，直到控制信号结束为止。 控制信号连接到控制元件的预充电输入，并且求和节点经由逆变器连接到一个或多个评估树和控制元件输出。 逆变器连接到超控电路，其将控制元件的输出强制到与预充电状态相反的状态，直到控制信号结束。 然后，控制元件的输出呈现与预充电状态相对应的状态，直到评估发生。 因此，控制元件输出产生指示控制信号的结束与评估之间的间隔的窗口信号。

公开(公告)号：US20060184852A1

公开(公告)日：2006-08-17

申请号：US11050351

申请日：2005-02-03

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： H04L1/00 ,  H03M13/00 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30

CPC分类号： G06F11/24

摘要： A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.

公开(公告)号：US20060155966A1

公开(公告)日：2006-07-13

申请号：US11324399

申请日：2006-01-03

申请人： William Burky ,  Peter Klim

发明人： William Burky ,  Peter Klim

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag. Each cell in the array has an output for each thread supported by the array, and the logic provides a flush mask output for each thread as well as a combined flush mask output that supports simultaneous access for all of the threads.

摘要翻译： 包括用于在多线程处理系统中计算闪存掩码的寄存器文件和方法的处理器响应于多个刷新请求源而提供刷新结果的快速和低逻辑开销计算。 刷新掩码寄存器文件由数组中的多个单元格实现，其中单元格不在对角线，其中列索引等于行索引。 每个单元都具有垂直写入使能和水平写入使能。 当一行写入以验证该行的标签值时，具有等于行选择器的索引的列将自动重置（除了与上述缺少的单元格相对应的位）。 在阵列中的一行读取中，每列提供的有线AND电路提供了与自行的最后一次复位以来写入的其他行相对应的位字段，该行是指示较新标记的刷新掩码，并且所选择的 标签。 数组中的每个单元格都具有数组支持的每个线程的输出，逻辑为每个线程提供了一个刷新掩码输出以及一个组合的刷新输出，支持所有线程的同时访问。

公开(公告)号：US20050099205A1

公开(公告)日：2005-05-12

申请号：US10703016

申请日：2003-11-06

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： G06F7/38 ,  G11C7/10 ,  H03K19/0175 ,  H03K19/173

CPC分类号： G11C7/1048 ,  G11C2207/007

摘要： A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.

摘要翻译： 寄存器 - 文件位读取装置包括：解码器，可操作用于接收多个地址位信号，并响应地在M个选择行之一中断言选择信号。 每个选择行对应于M个寄存器文件单元中的相应一个。 该装置还包括具有Q个输出节点和M个选择器的多路复用器。 每个选择器耦合到选择线之一，并选择线对应的寄存器文件单元。 选择器处于Q组中，每组耦合到多路复用器的输出节点中的相应一个。 该装置还包括具有Q输入的输出逻辑门，耦合到多路复用器输出节点中的相应一个。 多路复用器包括Q个上拉，其中每个Q上拉耦合到多路复用器输出节点中的相应一个，并且可操作以响应于地址位信号之一驱动其多路复用器输出节点。

公开(公告)号：US20070229132A1

公开(公告)日：2007-10-04

申请号：US11277691

申请日：2006-03-28

申请人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

发明人： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC分类号： H03K3/00

CPC分类号： H03K3/0375 ,  G01R31/318533 ,  G01R31/318536 ,  H03K3/013 ,  H03K3/356121 ,  H03K19/00392

摘要： A latch is described that provides soft error rate protection with integrated scan capability and collision avoidance. The latch has a latch output node and a first, second, and third sublatches. Each sublatch has a respective input circuitry, output node, and feedback circuitry coupled to the output node for reinforcing an output signal of the sublatch. Each sublatch is operable to receive a data signal at its input circuitry and responsively generate a binary-state output signal on its output nodes. The first and second output nodes such that, if an output of the third sublatch changes, the first and second sublatches force the third sublatch to have a same output. This “forced” change reduces the soft error rate in the latch and the output signal of the latch output node is restored without the sublatches colliding.

摘要翻译： 描述了提供具有集成扫描能力和避免碰撞的软错误率保护的锁存器。 闩锁具有闩锁输出节点和第一，第二和第三子实体。 每个分支具有相应的输入电路，输出节点和耦合到输出节点的反馈电路，用于加强子锁的输出信号。 每个子选项可操作以在其输入电路处接收数据信号，并在其输出节点上响应地生成二进制状态输出信号。 第一和第二输出节点使得如果第三个分支的输出发生变化，则第一和第二个分页强制第三个分块具有相同的输出。 这种“强制”改变降低了锁存器中的软错误率，并且恢复锁存器输出节点的输出信号，而不会使得副本碰撞。