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    Aggregated page fault signaling and handline
    1.
    发明授权
    Aggregated page fault signaling and handline 有权

    公开(公告)号：US09891980B2

    公开(公告)日：2018-02-13

    申请号：US13977106

    申请日：2011-12-29

    申请人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

    发明人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

    IPC分类号： G06F11/07 ,  G06F9/30 ,  G06F12/08

    CPC分类号： G06F11/0784 ,  G06F9/30036 ,  G06F9/30043 ,  G06F12/08

    摘要： A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

    Extension of CPU context-state management for micro-architecture state
    3.
    发明授权
    Extension of CPU context-state management for micro-architecture state 有权
    扩展用于微架构状态的CPU上下文状态管理

    公开(公告)号：US09361101B2

    公开(公告)日：2016-06-07

    申请号：US13538252

    申请日：2012-06-29

    申请人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

    发明人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

    IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30043 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/461

    摘要： A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

    摘要翻译： 处理器可以节省微架构上下文以提高代码执行和电源管理的效率。 执行保存指令以在停止进程的执行的上下文切换时将微架构状态和处理器的体系结构状态存储在存储器的公共缓冲器中。 微架构状态包含执行该过程所产生的性能数据。 执行恢复指令以在恢复执行该过程时从公共缓冲器检索微架构状态和架构状态。 电源管理硬件然后使用微架构状态作为恢复执行的中间起点。

    Techniques for management of shared resources in wireless multi-communication devices
    4.
    发明授权
    Techniques for management of shared resources in wireless multi-communication devices 有权
    无线多通信设备共享资源管理技术

    公开(公告)号：US08644202B2

    公开(公告)日：2014-02-04

    申请号：US13293637

    申请日：2011-11-10

    申请人： Boris Ginzburg ,  Sharon Ben-Porat ,  Oren Kaidar ,  Shlomo Avital ,  Avishay Sharaga ,  Sridharan Sakthivelu ,  Eran Friedlander

    发明人： Boris Ginzburg ,  Sharon Ben-Porat ,  Oren Kaidar ,  Shlomo Avital ,  Avishay Sharaga ,  Sridharan Sakthivelu ,  Eran Friedlander

    IPC分类号： H04W72/00 ,  H04W48/18

    CPC分类号： H04W76/15 ,  H04W48/16 ,  H04W72/00 ,  H04W76/28 ,  H04W88/06

    摘要： An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology, and wherein the network adapter is configured to share a plurality of shared hardware components by limiting access to the air to one comm only at given time by designating one comm that owns the shared hardware components as a primary comm and all other comms are secondary comms, wherein the primary comm allows the secondary comms to use the shared hardware components when it is in an idle-state but when the primary comm returns from the idle state, it claims ownership of the shared resources and the secondary comms release the shared resources.

    摘要翻译： 本发明的一个实施例提供了一种装置，其包括被配置用于使用多于一种技术的无线通信的网络适配器，并且其中所述网络适配器被配置为通过仅通过将访问空中限制到一个通信来共享多个共享硬件组件 给定时间通过指定一个拥有共享硬件组件作为主要通信的通信，所有其他通信是次要通信，其中主通信允许辅助通信在处于空闲状态时使用共享硬件组件，但是当主要通信 comm从空闲状态返回，它声明共享资源的所有权，次要通信释放共享资源。

    SYNCHRONOUS SOFTWARE INTERFACE FOR AN ACCELERATED COMPUTE ENGINE
    5.
    发明申请
    SYNCHRONOUS SOFTWARE INTERFACE FOR AN ACCELERATED COMPUTE ENGINE 审中-公开
    用于加速计算机发动机的同步软件接口

    公开(公告)号：US20130268804A1

    公开(公告)日：2013-10-10

    申请号：US13994371

    申请日：2011-12-30

    申请人： Ronny Ronen ,  Boris Ginzburg ,  Eliezer Weissmann

    发明人： Ronny Ronen ,  Boris Ginzburg ,  Eliezer Weissmann

    IPC分类号： G06F9/54 ,  G06F11/14

    CPC分类号： G06F11/0724 ,  G06F9/3881 ,  G06F9/4484 ,  G06F9/54 ,  G06F9/542 ,  G06F11/0793 ,  G06F11/1474

    摘要： Some implementations disclosed herein provide techniques and arrangements for a synchronous software interface for a specialized logic engine. The synchronous software interface may receive, from a first core of a plurality of cores, a control block including a transaction for execution by the specialized logic engine. The synchronous software interface may send the control block to the specialized logic engine and wait to receive a confirmation from the specialized logic engine that the transaction was successfully executed.

    摘要翻译： 本文中公开的一些实施例提供了用于专用逻辑引擎的同步软件接口的技术和布置。 同步软件接口可以从多个核心的第一核心接收包括专用逻辑引擎执行的事务的控制块。 同步软件接口可以将控制块发送到专用逻辑引擎，并等待从专门的逻辑引擎接收事务成功执行的确认。

    DYNAMIC PINNING OF VIRTUAL PAGES SHARED BETWEEN DIFFERENT TYPE PROCESSORS OF A HETEROGENEOUS COMPUTING PLATFORM
    8.
    发明申请
    DYNAMIC PINNING OF VIRTUAL PAGES SHARED BETWEEN DIFFERENT TYPE PROCESSORS OF A HETEROGENEOUS COMPUTING PLATFORM 有权
    异步计算平台的不同类型处理器之间共享的虚拟页面动态拼接

    公开(公告)号：US20130007406A1

    公开(公告)日：2013-01-03

    申请号：US13175489

    申请日：2011-07-01

    申请人： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

    发明人： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F12/0804 ,  G06F12/126 ,  G06F13/1663 ,  G06F2212/303 ,  G06F2212/657 ,  G06F2212/684

    摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

    摘要翻译： 计算机系统可以支持一种或多种技术来允许由非CPU设备（例如，图形处理单元，GPU）访问的存储器页的动态固定。 非CPU可以支持虚拟到物理地址映射，并且因此可以知道可能不被固定但可被非CPU访问的存储器页。 非CPU可以向诸如与CPU相关联的设备驱动程序的运行时组件通知或发送这样的信息。 在一个实施例中，设备驱动程序可以动态地执行可由非CPU访问的这种存储器页的钉扎。 设备驱动程序甚至可以取消内存页，这可能不再被非CPU访问。 这样的方法可以允许非CPU可以不再访问的存储器页面可用于分配给其他CPU和/或非CPU。

    Method for matching timing on high fanout signal paths using routing guides
    9.
    发明授权
    Method for matching timing on high fanout signal paths using routing guides 有权
    使用路由指南在高扇出信号路径上匹配定时的方法

    公开(公告)号：US08185860B2

    公开(公告)日：2012-05-22

    申请号：US13206449

    申请日：2011-08-09

    申请人： Michael Burstein ,  Boris Ginzburg ,  Andrew Nikishin

    发明人： Michael Burstein ,  Boris Ginzburg ,  Andrew Nikishin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5031 ,  G06F2217/84

    摘要： A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.

    摘要翻译： 公开了用于在电路设计中路由信号路径或电路块之间的连接的方法，算法，软件，架构和/或系统。 在一个实施例中，路由的方法可以包括：（i）确定至少三个电路块之间的信号路径; （ii）放置路线指引; 并且（iii）将信号路径路由通过路由引导，使得沿着两个或更多个电路块处的信号路径的信号的定时基本匹配。 电路块可以包括例如被配置为实现逻辑或定时功能的标准单元，其它组件和/或集成电路。 路由指南可以包括分配器，其被配置为将信号路径分支到至少两个相关联的段中。 本发明的实施例可以有利地改善在自动化位置和路由流中的电路块之间的高扇出信号路径的信号定时。

    Method for matching timing on high fanout signal paths using routing guides
    10.
    发明授权
    Method for matching timing on high fanout signal paths using routing guides 有权
    使用路由指南在高扇出信号路径上匹配定时的方法

    公开(公告)号：US08015533B1

    公开(公告)日：2011-09-06

    申请号：US10946926

    申请日：2004-09-21

    申请人： Michael Burstein ,  Boris Ginzburg ,  Andrew Nikishin

    发明人： Michael Burstein ,  Boris Ginzburg ,  Andrew Nikishin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5031 ,  G06F2217/84

    摘要： A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.

    摘要翻译： 公开了用于在电路设计中路由信号路径或电路块之间的连接的方法，算法，软件，架构和/或系统。 在一个实施例中，路由的方法可以包括：（i）确定至少三个电路块之间的信号路径; （ii）放置路线指引; 并且（iii）将信号路径路由通过路由引导，使得沿着两个或更多个电路块处的信号路径的信号的定时基本匹配。 电路块可以包括例如被配置为实现逻辑或定时功能的标准单元，其它组件和/或集成电路。 路由指南可以包括分配器，其被配置为将信号路径分支到至少两个相关联的段中。 本发明的实施例可以有利地改善在自动化位置和路由流中的电路块之间的高扇出信号路径的信号定时。