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1.发明授权Integrated circuit, system, and method including a shared synchronization bus 有权集成电路，系统和方法，包括共享同步总线公开(公告)号：US08914563B2
公开(公告)日：2014-12-16
申请号：US13407721
申请日：2012-02-28
CPC分类号： G06F13/385
摘要： An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.
摘要翻译： 集成电路包括具有分配给多个外围模块中的一个或多个的多个通道的共享同步总线。 集成电路还包括多个外围模块的第一外围模块，包括耦合到共享同步总线的控制输出，并且被配置为通过所选择的一个将事件定时数据传送到多个外围模块的第二外围模块的输入 的多个通道。
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2.发明申请Integrated Circuit, System, and Method Including a Shared Synchronization Bus 有权包括共享同步总线的集成电路，系统和方法公开(公告)号：US20130227181A1
公开(公告)日：2013-08-29
申请号：US13407721
申请日：2012-02-28
IPC分类号： G06F13/14
CPC分类号： G06F13/385
摘要： An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.
摘要翻译： 集成电路包括具有分配给多个外围模块中的一个或多个的多个通道的共享同步总线。 集成电路还包括多个外围模块的第一外围模块，包括耦合到共享同步总线的控制输出，并且被配置为通过所选择的一个将事件定时数据传送到多个外围模块的第二外围模块的输入 的多个通道。
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3.发明申请INTEGRATED CIRCUIT, MICRO-CONTROLLER UNIT, AND METHOD INCLUDING A SYNCHRONOUS SAMPLING CONTROLLER 有权集成电路，微控制器单元和包含同步采样控制器的方法公开(公告)号：US20130222027A1
公开(公告)日：2013-08-29
申请号：US13407708
申请日：2012-02-28
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.
摘要翻译： 微控制器单元（MCU）包括包括输入，定时输入和输出的模数转换器（ADC）。 ADC的输入可配置为耦合到外设模块的输出。 MCU还包括同步采样控制器，其被配置为向可配置为耦合到外围模块的时钟输入的时钟输出端提供时钟信号。 同步采样控制器还被配置为向ADC的定时输入提供定时信号，以将ADC的输入处的信号采样同步到外围模块的定时。
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4.发明授权Integrated circuit, micro-controller unit, and method including a synchronous sampling controller 有权集成电路，微控制器单元以及包括同步采样控制器的方法公开(公告)号：US08513989B1
公开(公告)日：2013-08-20
申请号：US13407708
申请日：2012-02-28
IPC分类号： H03L7/06
CPC分类号： H03L7/00
摘要： A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.
摘要翻译： 微控制器单元（MCU）包括包括输入，定时输入和输出的模数转换器（ADC）。 ADC的输入可配置为耦合到外设模块的输出。 MCU还包括同步采样控制器，其被配置为向可配置为耦合到外围模块的时钟输入的时钟输出端提供时钟信号。 同步采样控制器还被配置为向ADC的定时输入提供定时信号，以将ADC的输入处的信号采样同步到外围模块的定时。
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公开(公告)号：US20130222165A1
公开(公告)日：2013-08-29
申请号：US13407730
申请日：2012-02-28
IPC分类号： H03M1/66
CPC分类号： G06F3/005 , G06F3/05 , H04L7/0008
摘要： An integrated circuit includes a current-based digital-to-analog converter (IDAC) including a clock input and including an output. The integrated circuit further includes a sample synchronization generator to provide a clock signal to a clock output terminal and a first timing signal related to the clock signal to the clock input of the IDAC. The sample synchronization generator controls the clock signal and the first timing signal to communicate a control signal to a peripheral module.
摘要翻译： 集成电路包括基于电流的数模转换器（IDAC），其包括时钟输入并包括输出。 该集成电路还包括一个采样同步发生器，用于向时钟输出端提供时钟信号，以及一个与时钟信号相关的第一定时信号给IDAC的时钟输入。 采样同步发生器控制时钟信号和第一定时信号，以将控制信号传送到外围模块。
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公开(公告)号：US08629794B2
公开(公告)日：2014-01-14
申请号：US13407730
申请日：2012-02-28
IPC分类号： H03M1/66
CPC分类号： G06F3/005 , G06F3/05 , H04L7/0008
摘要： An integrated circuit includes a current-based digital-to-analog converter (IDAC) including a clock input and including an output. The integrated circuit further includes a sample synchronization generator to provide a clock signal to a clock output terminal and a first timing signal related to the clock signal to the clock input of the IDAC. The sample synchronization generator controls the clock signal and the first timing signal to communicate a control signal to a peripheral module.
摘要翻译： 集成电路包括基于电流的数模转换器（IDAC），其包括时钟输入并包括输出。 该集成电路还包括一个采样同步发生器，用于向时钟输出端提供时钟信号，以及一个与时钟信号相关的第一定时信号给IDAC的时钟输入。 采样同步发生器控制时钟信号和第一定时信号，以将控制信号传送到外围模块。
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公开(公告)号：US20120173775A1
公开(公告)日：2012-07-05
申请号：US12981021
申请日：2010-12-29
IPC分类号： G06F3/00
摘要： A method of controlling a port in an apparatus includes receiving an instruction for execution by a processor. The method further includes executing the instruction, by writing a value to a storage location corresponding to the port, and by initializing a count operation. The method further includes proceeding with the count operation until a final count value is reached, and providing to the port the value written to the storage location.
摘要翻译： 控制装置中的端口的方法包括接收处理器执行的指令。 该方法还包括通过向对应于该端口的存储位置写入值并通过初始化计数操作来执行该指令。 该方法还包括进行计数操作，直到达到最终计数值，并向端口提供写入存储位置的值。
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8.发明授权System and method for using network interface card reset pin as indication of lock loss of a phase locked loop and brownout condition 有权使用网络接口卡复位引脚作为锁相环和锁定状态的锁定丢失的指示的系统和方法公开(公告)号：US07536608B2
公开(公告)日：2009-05-19
申请号：US11934203
申请日：2007-11-02
IPC分类号： G06F11/00
CPC分类号： G06F13/387
摘要： A method for providing an indication from a network interface controller to a microcontroller is disclosed wherein upon occurrence of a particular condition within the network interface controller, an indication is provided from a reset pin of the network interface controller to the microcontroller unit. Upon receipt of the indication by the microcontroller unit, communications between the network interface controller and the microcontroller unit are inhibited.
摘要翻译： 公开了一种从网络接口控制器向微控制器提供指示的方法，其中当在网络接口控制器内发生特定状况时，从网络接口控制器的复位引脚向微控制器单元提供指示。 在微控制器单元接收到指示时，禁止了网络接口控制器和微控制器单元之间的通信。
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公开(公告)号：US08914564B2
公开(公告)日：2014-12-16
申请号：US12981021
申请日：2010-12-29
IPC分类号： G06F3/00 , G06F15/173 , G06F13/28
摘要： A method of controlling a port in an apparatus includes receiving an instruction for execution by a processor. The method further includes executing the instruction, by writing a value to a storage location corresponding to the port, and by initializing a count operation. The method further includes proceeding with the count operation until a final count value is reached, and providing to the port the value written to the storage location.
摘要翻译： 控制装置中的端口的方法包括接收处理器执行的指令。 该方法还包括通过向对应于该端口的存储位置写入值并通过初始化计数操作来执行该指令。 该方法还包括进行计数操作，直到达到最终计数值，并向端口提供写入存储位置的值。
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10.发明授权Ethernet controller with excess on-board flash for microcontroller interface 有权以太网控制器，具有多余的板载闪存，用于微控制器接口公开(公告)号：US07624157B2
公开(公告)日：2009-11-24
申请号：US10880921
申请日：2004-06-30
IPC分类号： G06F15/167 , G06F21/00
CPC分类号： H04L12/40013 , H04L49/90 , H04L49/901
摘要： A single chip network controller for interfacing between a physical network and a processing system on the media side of the network controller. The network controller includes a physical layer for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data from the network, and for receiving data from the network and decoding the received data. A media layer is provided for interfacing with the processing system for receiving data from the processing system for interface with the physical layer for encoding and transmission thereof and for receiving decoded data from the physical layer and providing access thereto by the processing system. An on-chip non-volatile memory is provided having a first portion associated with configuration information for configuring the operation of the physical layer and the media layer, and a second portion thereof that is accessible by the processing system on the media side of the network controller. A memory interface allows the processing system to interface with the second portion of the memory, such that the processing system has an expanded memory capability.
摘要翻译： 用于在物理网络和网络控制器的媒体侧的处理系统之间进行接口的单芯片网络控制器。 网络控制器包括物理层，用于接收用于传输到网络的数据并对接收的数据进行编码以便传输到其中并用于从网络接收数据，并用于从网络接收数据并对接收的数据进行解码。 提供了一种媒体层，用于与处理系统进行接口，用于从处理系统接收数据以与物理层进行接口以进行编码和传输，并从物理层接收解码的数据并提供处理系统的访问。 提供一种片上非易失性存储器，其具有与用于配置物理层和媒体层的操作的配置信息相关联的第一部分，以及其第二部分，其可由网络的媒体侧上的处理系统访问 控制器。 存储器接口允许处理系统与存储器的第二部分接口，使得处理系统具有扩展的存储器能力。
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