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1.发明申请INTEGRATED CIRCUIT, MICRO-CONTROLLER UNIT, AND METHOD INCLUDING A SYNCHRONOUS SAMPLING CONTROLLER 有权集成电路，微控制器单元和包含同步采样控制器的方法公开(公告)号：US20130222027A1
公开(公告)日：2013-08-29
申请号：US13407708
申请日：2012-02-28
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.
摘要翻译： 微控制器单元（MCU）包括包括输入，定时输入和输出的模数转换器（ADC）。 ADC的输入可配置为耦合到外设模块的输出。 MCU还包括同步采样控制器，其被配置为向可配置为耦合到外围模块的时钟输入的时钟输出端提供时钟信号。 同步采样控制器还被配置为向ADC的定时输入提供定时信号，以将ADC的输入处的信号采样同步到外围模块的定时。
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2.发明授权Integrated circuit, micro-controller unit, and method including a synchronous sampling controller 有权集成电路，微控制器单元以及包括同步采样控制器的方法公开(公告)号：US08513989B1
公开(公告)日：2013-08-20
申请号：US13407708
申请日：2012-02-28
IPC分类号： H03L7/06
CPC分类号： H03L7/00
摘要： A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.
摘要翻译： 微控制器单元（MCU）包括包括输入，定时输入和输出的模数转换器（ADC）。 ADC的输入可配置为耦合到外设模块的输出。 MCU还包括同步采样控制器，其被配置为向可配置为耦合到外围模块的时钟输入的时钟输出端提供时钟信号。 同步采样控制器还被配置为向ADC的定时输入提供定时信号，以将ADC的输入处的信号采样同步到外围模块的定时。
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3.发明授权Integrated circuit, system, and method including a shared synchronization bus 有权集成电路，系统和方法，包括共享同步总线公开(公告)号：US08914563B2
公开(公告)日：2014-12-16
申请号：US13407721
申请日：2012-02-28
CPC分类号： G06F13/385
摘要： An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.
摘要翻译： 集成电路包括具有分配给多个外围模块中的一个或多个的多个通道的共享同步总线。 集成电路还包括多个外围模块的第一外围模块，包括耦合到共享同步总线的控制输出，并且被配置为通过所选择的一个将事件定时数据传送到多个外围模块的第二外围模块的输入 的多个通道。
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4.发明申请Integrated Circuit, System, and Method Including a Shared Synchronization Bus 有权包括共享同步总线的集成电路，系统和方法公开(公告)号：US20130227181A1
公开(公告)日：2013-08-29
申请号：US13407721
申请日：2012-02-28
IPC分类号： G06F13/14
CPC分类号： G06F13/385
摘要： An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.
摘要翻译： 集成电路包括具有分配给多个外围模块中的一个或多个的多个通道的共享同步总线。 集成电路还包括多个外围模块的第一外围模块，包括耦合到共享同步总线的控制输出，并且被配置为通过所选择的一个将事件定时数据传送到多个外围模块的第二外围模块的输入 的多个通道。
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公开(公告)号：US08238068B2
公开(公告)日：2012-08-07
申请号：US12766301
申请日：2010-04-23
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , G01R31/002 , G01R31/2853
摘要： In an embodiment, an electrical over-stress (EOS) circuit includes a detection circuit coupled between first and second supply terminals and configured to detect a perturbation in a supply voltage potential between the first and second supply terminals or between a supply voltage potential and a pad voltage of a bond pad. The EOS circuit further includes an alert generation circuit configured to store data indicating an EOS event in response to detecting the perturbation.
摘要翻译： 在一个实施例中，电过应力（EOS）电路包括耦合在第一和第二电源端子之间的检测电路，并且被配置为检测第一和第二电源端子之间的电源电压电位或电源电压电位和 接合焊盘的焊盘电压。 EOS电路还包括警报生成电路，其被配置为响应于检测到扰动而存储指示EOS事件的数据。
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公开(公告)号：US20100271742A1
公开(公告)日：2010-10-28
申请号：US12766301
申请日：2010-04-23
CPC分类号： H02H9/046 , G01R31/002 , G01R31/2853
摘要： In an embodiment, an electrical over-stress (EOS) circuit includes a detection circuit coupled between first and second supply terminals and configured to detect a perturbation in a supply voltage potential between the first and second supply terminals or between a supply voltage potential and a pad voltage of a bond pad. The EOS circuit further includes an alert generation circuit configured to store data indicating an EOS event in response to detecting the perturbation.
摘要翻译： 在一个实施例中，电过应力（EOS）电路包括耦合在第一和第二电源端子之间的检测电路，并且被配置为检测第一和第二电源端子之间的电源电压电位或电源电压电位和 接合焊盘的焊盘电压。 EOS电路还包括警报生成电路，其被配置为响应于检测到扰动而存储指示EOS事件的数据。
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公开(公告)号：US6034562A
公开(公告)日：2000-03-07
申请号：US442742
申请日：1995-05-17
申请人： Luis Augusto Bonet , Alan Lee Westwick , Mauricio Arturo Zavaleta , James Alan Tuvell , David E. Bush , Michael Dale Floyd
发明人： Luis Augusto Bonet , Alan Lee Westwick , Mauricio Arturo Zavaleta , James Alan Tuvell , David E. Bush , Michael Dale Floyd
摘要： A mixed signal processing system (22) includes digital (28) and analog (29) systems and is powered by a variable external voltage, such as a battery voltage. A voltage regulator (41) regulates the battery voltage to a nominal potential less than the battery voltage. The voltage regulator (41) provides the regulated voltage to a digital subsystem (51) of the digital system (28). A regulated charge pump (43) provides a voltage which is above the battery voltage and substantially constant due to regulation. The regulated charge pump (43) provides the regulated charge-pumped voltage to an analog subsystem (61) of the analog system (29) for better analog operation. A level shifter (44) equalizes signal levels between the digital (28) and analog (29) systems.
摘要翻译： 混合信号处理系统（22）包括数字（28）和模拟（29）系统，并且由诸如电池电压的可变外部电压供电。 电压调节器（41）将电池电压调节到小于电池电压的标称电位。 电压调节器（41）将调节的电压提供给数字系统（28）的数字子系统（51）。 调节电荷泵（43）提供高于电池电压并且由于调节而基本上恒定的电压。 调节电荷泵（43）将调节的电荷泵送电压提供给模拟系统（29）的模拟子系统（61），以实现更好的模拟操作。 电平移位器（44）使数字（28）和模拟（29）系统之间的信号电平相等。
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公开(公告)号：US5945878A
公开(公告)日：1999-08-31
申请号：US24482
申请日：1998-02-17
CPC分类号： H03F3/265 , H03F3/193 , H03F2200/492
摘要： A single-ended to differential converter (400, 500) has an input terminal (418, 518) which is adapted to be coupled to an inductance (412, 512). A first transistor (402, 502) which terminates an input signal received at the input terminal according to its transconductance has a first current electrode coupled to the input terminal. A second current electrode of the first transistor (402, 502) outputs one current of a differential output current. A second transistor (404, 504) has a control electrode coupled to the input terminal, a first current electrode coupled to a signal ground terminal, and a second current electrode for providing another current of the differential output current. Bias circuits bias the control electrodes of the first (402, 502) and second (404, 504) transistors to maintain the same DC currents through their current electrodes. The single-ended to differential converter (400, 500) reflects the noise produced by the first transistor (402, 502) in the second transistor (404, 504), and this common-mode noise can be rejected in a subsequent stage.
摘要翻译： 单端到差分转换器（400,500）具有适于耦合到电感（412,512）的输入端（418,518）。 根据其跨导终止在输入端接收的输入信号的第一晶体管（402,502）具有耦合到输入端的第一电流电极。 第一晶体管（402,502）的第二电流电极输出差分输出电流的一个电流。 第二晶体管（404,504）具有耦合到输入端子的控制电极，耦合到信号接地端子的第一电流电极和用于提供差分输出电流的另一电流的第二电流电极。 偏置电路偏置第一（402,502）和第二（404,504）晶体管的控制电极，以保持相同的直流电流通过其电流电极。 单端至差分转换器（400,500）反映由第二晶体管（404,504）中的第一晶体管（402,502）产生的噪声，并且该共模噪声可以在后续阶段被拒绝。
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