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1.发明申请公开(公告)号：US20110246746A1
公开(公告)日：2011-10-06
申请号：US12750448
申请日：2010-03-30
IPC分类号： H01L23/538 , H01L21/50 , G06F15/76 , G06F9/02
CPC分类号： H01L25/0652 , G06F13/385 , G11C5/02 , H01L23/3128 , H01L23/481 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555
摘要： Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.
摘要翻译： 各种实施例包括在接口管芯上形成骰子堆叠的装置，堆叠装置和方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。
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2.发明授权Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same 有权能够实现接口管芯和多个管芯堆叠之间的并发通信的装置，堆叠式器件中的交错导电路径以及用于形成和操作该管芯的方法公开(公告)号：US09123552B2
公开(公告)日：2015-09-01
申请号：US12750448
申请日：2010-03-30
CPC分类号： H01L25/0652 , G06F13/385 , G11C5/02 , H01L23/3128 , H01L23/481 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555
摘要： Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.
摘要翻译： 各种实施例包括在接口管芯上形成骰子堆叠的装置，堆叠装置和方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。
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3.发明授权Method and circuit for off chip driver control, and memory device using same 失效用于芯片外驱动器控制的方法和电路，以及使用其的存储器件公开(公告)号：US07463052B2
公开(公告)日：2008-12-09
申请号：US11351047
申请日：2006-02-08
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.
摘要翻译： 芯片外驱动器阻抗调整电路包括适于接收和存储驱动强度调节字的存储电路。 计数器电路耦合到存储电路以接收驱动强度调节字，并响应于驱动强度调整字产生驱动强度计数。 可编程保险丝代码来预设计数器。 输出驱动器电路耦合到计数器电路以接收驱动强度计数并且适于接收数据信号。 输出驱动器电路根据数据信号在输出端产生输出信号，并根据驱动强度计数调整驱动强度。
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4.发明授权Method and circuit for off chip driver control, and memory device using same 失效用于芯片外驱动器控制的方法和电路，以及使用其的存储器件公开(公告)号：US07019553B2
公开(公告)日：2006-03-28
申请号：US10726312
申请日：2003-12-01
IPC分类号： H03K19/03
CPC分类号： H03K19/0005
摘要： An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.
摘要翻译： 芯片外驱动器阻抗调整电路包括适于接收和存储驱动强度调节字的存储电路。 计数器电路耦合到存储电路以接收驱动强度调节字，并响应于驱动强度调整字产生驱动强度计数。 可编程保险丝代码来预设计数器。 输出驱动器电路耦合到计数器电路以接收驱动强度计数并且适于接收数据信号。 输出驱动器电路根据数据信号在输出端产生输出信号，并根据驱动强度计数调整驱动强度。
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公开(公告)号：US06691214B1
公开(公告)日：2004-02-10
申请号：US09650079
申请日：2000-08-29
申请人： Wen Li , Christopher K. Morzano
发明人： Wen Li , Christopher K. Morzano
IPC分类号： G06F1200
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1006 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2254
摘要： A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.
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6.发明授权Method and apparatus for testing cells in a memory device with compressed data and for replacing defective cells 有权用于使用压缩数据测试存储器件中的单元并用于替换有缺陷的单元的方法和装置公开(公告)号：US06202179B1
公开(公告)日：2001-03-13
申请号：US09333999
申请日：1999-06-15
IPC分类号： G11C2900
摘要： A compression test mode, independent of redundancy, for a memory device is disclosed. In one embodiment, a method for testing a memory array of a memory device includes outputting individually the output bits of a predetermined number of memory cells, upon failure of a compression mode. The cells may then be checked for errors and replaced if necessary on an individual basis. In another embodiment, a memory device includes an array of memory cells, and a compression test mode circuit such that only those cells that are defective are replaced with redundant cells. The circuit checks a number of memory cells at one time, however, in a compression test mode.
摘要翻译： 公开了一种独立于存储器件的冗余的压缩测试模式。 在一个实施例中，用于测试存储器件的存储器阵列的方法包括在压缩模式失败时分别输出预定数量的存储器单元的输出位。 然后可以检查细胞的错误，并在必要时根据个体进行更换。 在另一个实施例中，存储器件包括存储器单元阵列和压缩测试模式电路，使得只有那些有故障的单元被替换为冗余单元。 然而，在压缩测试模式下，电路一次检查多个存储单元。
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公开(公告)号：US5913928A
公开(公告)日：1999-06-22
申请号：US853263
申请日：1997-05-09
摘要： A method and circuit for testing cells in a memory device is disclosed. Data is written to the cells and then the cells are read in groups. For example, groups of four cells are read together. Output bits of the four cells are compressed in a compression circuit to generate compressed data, and the compressed data is checked to determine if one or more of the four cells was defective and produced an incorrect output bit. If one of the cells was defective, each cell is read in a sequence and its output bit is tested to determine which of the four cells is defective. The defective cell is replaced with a redundant cell.
摘要翻译： 公开了一种用于测试存储器件中的单元的方法和电路。 将数据写入单元格，然后单元读取。 例如，四个单元格的组一起读取。 四个单元的输出位在压缩电路中被压缩以产生压缩数据，并且检查压缩数据以确定四个单元中的一个或多个是否有故障并产生不正确的输出位。 如果其中一个单元有缺陷，则按顺序读取每个单元，并测试其输出位以确定四个单元中的哪一个是有缺陷的。 有缺陷的单元被替换为冗余单元。
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公开(公告)号：US5680425A
公开(公告)日：1997-10-21
申请号：US535662
申请日：1995-09-28
CPC分类号： H04L49/3081 , H04L49/106 , H04L49/108 , H04L49/1553 , H04L49/255 , H04L49/30 , H04Q11/0478 , H04L2012/5674
摘要： A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferring a cell, or when another port is transferring a cell on a channel that conflicts with the channel attached to the port. The counter counts the appropriate number of digits corresponding to the length of the cell whereupon the port is provided with a signal indicating that the transmission has ended. In association with other control signals, the port may then begin transmitting a new cell. When multiple switches are attached to the same channel, the counter serves as a self-queuing mechanism that relieves a central controller from having to keep track of the transmission of bits by each port, and from having to select the next port for transmission.
摘要翻译： 多端口开关缓冲并传输数字数据单元。 它提供以分布式方式控制端口同步的能力。 每个端口与计数器相关联，该计数器在与其相关联的端口进行传输时正在传输单元，或者当另一端口正在传输与连接到端口的通道冲突的通道上的单元时开始计数。 计数器对与单元的长度相对应的适当的位数进行计数，由此端口被提供有指示传输已经结束的信号。 与其他控制信号相关联，端口然后可以开始发送新的小区。 当多个交换机连接到相同的信道时，该计数器用作自排队机制，可以减轻中央控制器不必跟踪每个端口的位传输，而不必选择下一个端口进行传输。
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9.发明授权Method and circuit for off chip driver control, and memory device using same 有权用于芯片外驱动器控制的方法和电路，以及使用其的存储器件公开(公告)号：US07936181B2
公开(公告)日：2011-05-03
申请号：US12329132
申请日：2008-12-05
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.
摘要翻译： 芯片外驱动器阻抗调整电路包括适于接收和存储驱动强度调节字的存储电路。 计数器电路耦合到存储电路以接收驱动强度调节字，并响应于驱动强度调整字产生驱动强度计数。 可编程保险丝代码来预设计数器。 输出驱动器电路耦合到计数器电路以接收驱动强度计数并且适于接收数据信号。 输出驱动器电路根据数据信号在输出端产生输出信号，并根据驱动强度计数调整驱动强度。
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10.发明授权Data strobe synchronization circuit and method for double data rate, multi-bit writes 有权数据选通同步电路和方法，用于双倍数据速率，多位写入公开(公告)号：US07561477B2
公开(公告)日：2009-07-14
申请号：US12077878
申请日：2008-03-20
申请人： Christopher K. Morzano , Wen Li
发明人： Christopher K. Morzano , Wen Li
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C11/4076 , G11C11/4094
摘要： A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.
摘要翻译： 数据选通同步电路包括接收全局数据选通脉冲的第一和第二逻辑电路和相应的使能信号。 控制电路首先向第一逻辑电路施加使能信号，使得第一逻辑电路响应于每个全局数据选通脉冲产生第一数据选通脉冲。 控制电路接收写入控制信号。 当写入控制信号变为有效时，控制电路终止施加到第一逻辑电路的使能信号并向第二逻辑电路施加使能信号。 然后，第二逻辑电路响应于下一个全局数据选通脉冲产生第二数据选通脉冲。 第一和第二数据选通脉冲用于锁存相应触发器中的数据信号。 数据选通脉冲可以在数据选通脉冲的前沿和后沿成对的触发器锁存数据信号。
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