公开(公告)号：US20060069830A1

公开(公告)日：2006-03-30

申请号：US10954809

申请日：2004-09-30

申请人： William Moyer ,  Jimmy Gumulja ,  Brett Murdock

发明人： William Moyer ,  Jimmy Gumulja ,  Brett Murdock

IPC分类号： G06F13/00

CPC分类号： G06F13/362

摘要： A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is beings accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

摘要翻译： 总线主控器可以基于当前挂起的访问的一个或多个特征来选择性地撤回当前未决的访问。 以这种方式，总线主控可以更好地控制其访问请求。 一个或多个特征可以包括例如访问的类型（例如读/写，指令/数据，突发/非突发等），访问的顺序或顺序，被访问的地址（例如哪个地址范围是 访问的或哪个设备被访问），总线主机请求撤回（在例如多主机系统中）或其任何组合。 总线仲裁器还可以基于当前待决的访问请求或后续访问请求的一个或多个特征来选择性地撤回当前待决的访问请求，以有利于后续的访问请求。 这些特征可以包括上面列出的任何一个，请求主机的优先级（例如请求主机之间的优先级增量），请求主机的其他属性或其任何组合。

公开(公告)号：US20050060455A1

公开(公告)日：2005-03-17

申请号：US10660845

申请日：2003-09-12

申请人： Brett Murdock ,  William Moyer

发明人： Brett Murdock ,  William Moyer

IPC分类号： G06F12/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/40

CPC分类号： G06F13/4031 ,  G06F13/4022

摘要： An arbitration control circuit (11) for arbitrating access to a slave device (4) by a plurality of master devices (2, 3) includes an undefined length burst (ULB) arbitration logic circuit (12). The ULB arbitration logic circuit (12) includes a counter (26) and a control register (24). The control register (24) stores a predetermined value. During a ULB access of the slave device (4), the counter (26) is loaded with the predetermined value and is decremented for each beat of the undefined length burst access. Arbitration access beats during the undefined length burst access.

摘要翻译： 用于仲裁由多个主设备（2,3）访问从设备（4）的仲裁控制电路（11）包括未定义的长度突发（ULB）仲裁逻辑电路（12）。 ULB仲裁逻辑电路（12）包括计数器（26）和控制寄存器（24）。 控制寄存器（24）存储预定值。 在从设备（4）的ULB接入期间，计数器（26）被加载预定值，并且对于未定义的长度突发存取的每个节拍而递减。 仲裁访问在未定义的长度突发访问期间跳动。

公开(公告)号：US20050273544A1

公开(公告)日：2005-12-08

申请号：US11203935

申请日：2005-08-15

申请人： Michael Fitzsimmons ,  William Moyer ,  Brett Murdock

发明人： Michael Fitzsimmons ,  William Moyer ,  Brett Murdock

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

摘要翻译： 交叉开关（12）仲裁用于从多个总线主机（14,16,18,20和22）到具有重叠地址范围的多个寻址从端口（3和4）的访问。 在一种形式中，地址范围是相同的地址范围。 当所有寻址端口都忙时，交叉开关（12）使用共享从端口控制电路（48），配置寄存器（46）和从端口仲裁器逻辑（34,36,38,40,42和44）仲裁访问 。 确定新的访问请求是否比现有访问的优先级更高或更低。 基于对包括所请求的数据跳动的数量以及等待状态信息的各种因素的预测，首先将确定某个多个访问中的哪一个将首先完成，从而确定何时引导新的访问请求。 在一种模式中，动态地确定等待状态信息。

公开(公告)号：US20070186217A1

公开(公告)日：2007-08-09

申请号：US11347103

申请日：2006-02-03

申请人： Brett Murdock ,  William Moyer ,  Benjamin Eckermann

发明人： Brett Murdock ,  William Moyer ,  Benjamin Eckermann

IPC分类号： G06F9/46

CPC分类号： G06F13/14 ,  G06F13/36

摘要： A method includes receiving, at an interconnect, a first transaction request from a first requesting module. The first transaction request includes a request to utilize at least one system resource accessible via the interconnect. The method further includes determining potential interferences at the interconnect expected to occur as a result of a utilization of the at least one system resource by the first requesting module and initiating processing of the first transaction request at the interconnect. The method additionally includes authorizing processing of a second transaction request from a second requesting module during the processing of the first transaction request based on the determined potential interferences.

摘要翻译： 一种方法包括在互连处从第一请求模块接收第一事务请求。 第一交易请求包括利用经由互连可访问的至少一个系统资源的请求。 该方法还包括确定作为由第一请求模块利用至少一个系统资源并且在互连处开始处理第一事务请求的结果期望发生的互连处的潜在干扰。 该方法另外包括基于所确定的潜在干扰，在第一交易请求的处理期间授权处理来自第二请求模块的第二交易请求。

公开(公告)号：US20060277349A1

公开(公告)日：2006-12-07

申请号：US11142148

申请日：2005-06-01

申请人： Brett Murdock ,  William Moyer ,  Michael Fitzsimmons

发明人： Brett Murdock ,  William Moyer ,  Michael Fitzsimmons

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transactions, or use to index storage locations that indicate priority values. The transaction identifiers can be selected to be associated with a transaction by the requesting device or other priority determination module based upon predefined criteria.

摘要翻译： 公开了一种方法，其中基于与每个交易相关联的交易标识符来确定能够在公共时间处理的交易中的优先级。 事务标识符可以直接指示事务之间的优先级，或用于索引指示优先级值的存储位置。 可以基于预定义的标准，将请求设备或其他优先级确定模块的交易标识符选择为与交易相关联。

公开(公告)号：US20060069839A1

公开(公告)日：2006-03-30

申请号：US10955558

申请日：2004-09-30

申请人： William Moyer ,  Brett Murdock

发明人： William Moyer ,  Brett Murdock

IPC分类号： G06F13/36

CPC分类号： G06F13/368

摘要： A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

公开(公告)号：US20050027920A1

公开(公告)日：2005-02-03

申请号：US10631167

申请日：2003-07-31

申请人： Michael Fitzsimmons ,  William Moyer ,  Brett Murdock

发明人： Michael Fitzsimmons ,  William Moyer ,  Brett Murdock

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

摘要翻译： 交叉开关（12）仲裁用于从多个总线主机（14,16,18,20和22）到具有重叠地址范围的多个寻址从端口（3和4）的访问。 在一种形式中，地址范围是相同的地址范围。 当所有寻址端口都忙时，交叉开关（12）使用共享从端口控制电路（48），配置寄存器（46）和从端口仲裁器逻辑（34,36,38,40,42和44）仲裁访问 。 确定新的访问请求是否比现有访问的优先级更高或更低。 基于对包括所请求的数据跳动的数量以及等待状态信息的各种因素的预测，首先将确定某个多个访问中的哪一个将首先完成，从而确定何时引导新的访问请求。 在一种模式中，动态地确定等待状态信息。

公开(公告)号：US20050193256A1

公开(公告)日：2005-09-01

申请号：US11099889

申请日：2005-04-06

申请人： William Moyer

发明人： William Moyer

IPC分类号： G06F11/00

CPC分类号： G06F11/349 ,  G06F11/3485 ,  G06F11/3636

摘要： A data processing system (10) has a debug module (26) that selectively generates one or more debug messages that are specific to a Direct Memory Access (DMA) controller device (16) in the system. A control register(70) enables which of the DMA debug messages are provided. The beginning and end of DMA transfer activity is provided including when minor loop iterations start and complete. Latency information indicating system latency between a channel request and actual initiation of the request for each DMA transfer may also be included in a debug message. One of the debug messages provides periodic status of a predetermined DMA channel under control of a control register (80). At least one of the debug messages implements a watchpoint function, such as indicating when a transfer starts or ends. The debug module may be centralized in the system or distributed among each of predetermined system units.

摘要翻译： 数据处理系统（10）具有调试模块（26），其选择性地生成系统中特定于直接存储器访问（DMA）控制器设备（16）的一个或多个调试消息。 控制寄存器（70）使得能够提供哪个DMA调试消息。 提供DMA传输活动的开始和结束，包括在次循环迭代开始和完成时。 指示信道请求与每个DMA传送的请求的实际启动之间的系统等待时间的延迟信息也可以被包括在调试消息中。 一个调试消息在控制寄存器（80）的控制下提供预定DMA通道的周期状态。 至少一个调试消息实现观察点功能，例如指示传输何时开始或结束。 调试模块可以集中在系统中或分布在每个预定系统单元之间。

公开(公告)号：US20050055543A1

公开(公告)日：2005-03-10

申请号：US10657510

申请日：2003-09-05

申请人： William Moyer

发明人： William Moyer

IPC分类号： G06F9/44

CPC分类号： G06F9/30043 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30069 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/325 ,  G06F9/345 ,  G06F9/3455

摘要： Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned- extended when transferred.

摘要翻译： 可以使用各种加载和存储指令来在寄存器文件和存储器中的寄存器之间传送多个向量元素。 可以使用cnt参数来指示要传送到存储器或从存储器传送的元素的总数，并且可以使用rcnt参数来指示可以传送到寄存器文件中的单个寄存器的向量元素的最大数量 。 此外，指令可以使用各种不同的寻址模式。 可以独立于寄存器元件大小指定存储器元件大小，使得源和目标大小在指令内可能不同。 通过一些指令，可以启动向量流并有条件地排队或出队。 可以提供截断或舍入字段，使得源数据元素在被传送时可以被截断或舍入。 此外，源数据元素在传输时可以是符号或无符号扩展的。

公开(公告)号：US20050055534A1

公开(公告)日：2005-03-10

申请号：US10657593

申请日：2003-09-08

申请人： William Moyer

发明人： William Moyer

IPC分类号： G06F9/312 ,  G06F9/318 ,  G06F15/00

CPC分类号： G06F9/30043 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30181 ,  G06F9/3455

摘要： Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.

摘要翻译： 可以使用各种加载和存储指令来在寄存器文件和存储器中的寄存器之间传送多个向量元素。 可以使用cnt参数来指示要传送到存储器或从存储器传送的元素的总数，并且可以使用rcnt参数来指示可以传送到寄存器文件中的单个寄存器的向量元素的最大数量 。 此外，指令可以使用各种不同的寻址模式。 可以独立于寄存器元件大小指定存储器元件大小，使得源和目标大小在指令内可能不同。 通过一些指令，可以启动向量流并有条件地排队或出队。 可以提供截断或舍入字段，使得源数据元素在被传送时可以被截断或舍入。 此外，源数据元素在传输时可以是符号或无符号扩展的。