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    PROCESSING UNIT WITH CROSS-COUPLED ALUS/ACCUMULATORS AND INPUT DATA FEEDBACK STRUCTURE INCLUDING CONSTANT GENERATOR AND BYPASS TO REDUCE MEMORY CONTENTION
    3.
    发明申请
    PROCESSING UNIT WITH CROSS-COUPLED ALUS/ACCUMULATORS AND INPUT DATA FEEDBACK STRUCTURE INCLUDING CONSTANT GENERATOR AND BYPASS TO REDUCE MEMORY CONTENTION 失效
    具有交叉耦合ALUS /累加器的加工单元和输入数据反馈结构，包括恒定发电机和旁路以减少存储器内容

    公开(公告)号：US20050228970A1

    公开(公告)日：2005-10-13

    申请号：US10209109

    申请日：2002-07-30

    申请人： Shuhua Xiang ,  Li Sha ,  Ping Zhu ,  Hongjun Yuan ,  Wei Ni

    发明人： Shuhua Xiang ,  Li Sha ,  Ping Zhu ,  Hongjun Yuan ,  Wei Ni

    IPC分类号： G06F7/57 ,  G06F9/38 ,  G06F15/00

    CPC分类号： G06F9/3867 ,  G06F7/57 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3885

    摘要： A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.

    摘要翻译： 处理系统包括算术逻辑单元（ALU）子系统，其允许与先前指令相关联的数据被保留以用于下一个指令或后续指令，而不必使用中间寄存器重新加载该值。 ALU子系统包括与一对蓄能器通信地交叉耦合的一对ALU。 处理系统还包括耦合到ALU子系统以与存储器争用预测一起使用的数据选择器。 数据选择器包括恒定发生器，其控制与旁路元件中的先前指令相关联的数据的存储，以及选择器，用于在数据总线元件的数据和存储在旁路元件中的数据之间进行选择。

    CELL ARRAY AND METHOD OF MULTIRESOLUTION MOTION ESTIMATION AND COMPENSATION
    4.
    发明申请
    CELL ARRAY AND METHOD OF MULTIRESOLUTION MOTION ESTIMATION AND COMPENSATION 失效
    细胞阵列和多元运动估计和补偿方法

    公开(公告)号：US20050213661A1

    公开(公告)日：2005-09-29

    申请号：US09924079

    申请日：2001-08-07

    申请人： Shuhua Xiang ,  Li Sha ,  Yaojun Luo

    发明人： Shuhua Xiang ,  Li Sha ,  Yaojun Luo

    IPC分类号： G06T7/20 ,  H04N5/14 ,  H04N7/12 ,  H04N7/18 ,  H04N7/26

    CPC分类号： H04N19/523 ,  G06T7/223 ,  G06T2207/10016 ,  H04N5/145 ,  H04N19/43 ,  H04N19/53

    摘要： A method, apparatus, computer medium, and other embodiments for motion estimation and compensation processing of video and image signals are described. Within a sequence of frames, block-based differences are taken between frames to exploit redundancies between pictures by taking a matchblock from the current picture and by determining a spatial offset in a corresponding reference picture which signifies a good prediction of where the current macroblock can be found. Multi-level motion estimation is performed in three stages to refine the resolution of the motion vector with reduced computational bandwidth. First, a matchblock from a reference frame is decomposed equally into several sub-matchblocks, each of which is searched in parallel over a search area decomposed into sub-blocks by a similar factor so as to determine a preliminary motion vector in the reference picture. Second, a full size matchblock is then searched over a refined search area using the preliminary motion vector to determine an intermediate motion vector, so as to refine the resolution of the preliminary motion vector. Third, fractional-pixel searching is then performed on the matchblock and the intermediate motion vector to determine a final motion vector having an even higher resolution associated with the best motion vector to be used in predicting the current macroblock. In one embodiment, a processor-based motion estimation and compensation cell array enables contemporaneous and independent loading and processing operations in parallel.

    摘要翻译： 描述了用于视频和图像信号的运动估计和补偿处理的方法，装置，计算机介质和其它实施例。 在一系列帧内，在帧之间采用基于块的差异，以通过从当前图像获取匹配块并且通过确定相应参考图片中的空间偏移来表示图像之间的冗余，其表示对当前宏块可以在何处的良好预测 发现。 多级运动估计分三个阶段进行，以减少计算带宽的细化运动矢量的分辨率。 首先，来自参考帧的匹配块被分解为几个子匹配块，每个子块通过相似的因素并行地搜索到被分解成子块的搜索区域，以便确定参考图片中的初步运动矢量。 其次，使用初步运动向量，在精细搜索区域上搜索全尺寸匹配块，以确定中间运动矢量，以便精细化预备运动矢量的分辨率。 第三，然后对匹配块和中间运动矢量执行分数像素搜索，以确定具有与用于预测当前宏块的最佳运动矢量相关联的更高分辨率的最终运动矢量。 在一个实施例中，基于处理器的运动估计和补偿单元阵列能够并行地实现同时且独立的加载和处理操作。

    Processing rasterized data
    5.
    发明授权
    Processing rasterized data 有权

    公开(公告)号：US08477146B2

    公开(公告)日：2013-07-02

    申请号：US12511238

    申请日：2009-07-29

    申请人： Shuhua Xiang ,  Li Sha ,  Ching-Han Tsai

    发明人： Shuhua Xiang ,  Li Sha ,  Ching-Han Tsai

    IPC分类号： G06T9/00 ,  G06F12/02 ,  G06F12/10

    CPC分类号： H04N19/423 ,  H04N19/433 ,  H04N19/44 ,  H04N19/61

    摘要： Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

    Systems and methods for image coding and processing
    6.
    发明授权
    Systems and methods for image coding and processing 有权
    图像编码和处理的系统和方法

    公开(公告)号：US08363969B1

    公开(公告)日：2013-01-29

    申请号：US12534632

    申请日：2009-08-03

    申请人： Haohong Wang ,  Li Sha

    发明人： Haohong Wang ,  Li Sha

    IPC分类号： G06K9/36

    CPC分类号： H04N19/423 ,  H04N19/12 ,  H04N19/126 ,  H04N19/13 ,  H04N19/15 ,  H04N19/18 ,  H04N19/184 ,  H04N19/30

    摘要： Embodiments of the present invention include systems and methods for processing and coding image data. In one embodiment, image data is coded using a first image coding process. If a bit rate constraint is satisfied, the image data is output. If the bit rate constraint is not satisfied, the image data is coded using a second different coding process. In one embodiment, the second coding process is a layered coding process. In another embodiment, if the constraint is satisfied, quantization data may be included in the output, and may be coded using layered coding. Variable length coding processes and hardware implementations are further disclosed for efficient image processing.

    摘要翻译： 本发明的实施例包括用于处理和编码图像数据的系统和方法。 在一个实施例中，使用第一图像编码处理对图像数据进行编码。 如果满足比特率约束，则输出图像数据。 如果不满足比特率约束，则使用第二不同的编码处理对图像数据进行编码。 在一个实施例中，第二编码处理是分层编码处理。 在另一个实施例中，如果约束被满足，量化数据可以被包括在输出中，并且可以使用分层编码进行编码。 进一步公开了可变长度编码处理和硬件实现用于有效的图像处理。

    DCS control module for a transformer in nuclear power engineering
    7.
    发明授权
    DCS control module for a transformer in nuclear power engineering 有权
    用于核电工程变压器的DCS控制模块

    公开(公告)号：US08229601B2

    公开(公告)日：2012-07-24

    申请号：US12839798

    申请日：2010-07-20

    申请人： Li Yang ,  Hongjian Tang ,  Shaoyong Wang ,  Li Sha ,  Huamin Chen ,  Chuangshu Xie ,  Jingshan Liu

    发明人： Li Yang ,  Hongjian Tang ,  Shaoyong Wang ,  Li Sha ,  Huamin Chen ,  Chuangshu Xie ,  Jingshan Liu

    IPC分类号： G05D3/12

    CPC分类号： G21D3/008 ,  G05B9/02 ,  Y02E30/40

    摘要： A distribution control system (DCS) control module for a transformer in nuclear power engineering, includes: an input command processing logic unit (1), a malfunction processing logic unit (2), a state processing logic unit (3), an output command generating logic unit (4) and a 6.6 kV switchgear of the transformer. The DCS control module utilizes the DCS integral with the power units to realize the control of 6.6 kV transformer switch, the sharing of the operator station with the power unit control system, and the overall monitoring, and the operation reliability of the power units is improved.

    摘要翻译： 一种用于核电工程变压器的配电控制系统（DCS）控制模块，包括：输入指令处理逻辑单元（1），故障处理逻辑单元（2），状态处理逻辑单元（3），输出指令 生成逻辑单元（4）和变压器的6.6 kV开关柜。 DCS控制模块利用与功率单元集成的DCS，实现6.6 kV变压器开关的控制，操作站与功率单元控制系统的共享，整体监控，动力单元的运行可靠性得到改善 。

    Multiple format video compression
    8.
    发明授权
    Multiple format video compression 失效
    多格式视频压缩

    公开(公告)号：US07085320B2

    公开(公告)日：2006-08-01

    申请号：US09953053

    申请日：2001-09-14

    申请人： He Ouyang ,  Li Sha ,  Shuhua Xiang ,  Yaojun Luo ,  Weimin Zeng ,  Jun Ding

    发明人： He Ouyang ,  Li Sha ,  Shuhua Xiang ,  Yaojun Luo ,  Weimin Zeng ,  Jun Ding

    IPC分类号： H04B7/12

    CPC分类号： H04N21/440218 ,  H04N19/12 ,  H04N19/40 ,  H04N19/42 ,  H04N19/61

    摘要： A video compression scheme enables the user to select one of many video compression formats, including the widely-used standard video formats such as MPEG-1, MPEG-2, MPEG-4 and H.263. In one embodiment, the scheme is implemented as a hardware-software combination, with the hardware portion, preferably implemented as an ASIC chip, performing the core compression and the software portion dealing with the detailed formatting. In another embodiment, a 32-bit aligned transitional data format is used.

    摘要翻译： 视频压缩方案使得用户能够选择许多视频压缩格式之一，包括广泛使用的标准视频格式，如MPEG-1，MPEG-2，MPEG-4和H.263。 在一个实施例中，该方案被实现为硬件 - 软件组合，硬件部分优选地实现为ASIC芯片，执行核心压缩以及处理详细格式化的软件部分。 在另一个实施例中，使用32位对齐的过渡数据格式。

    Video processing architecture definition by function graph methodology
    9.
    发明申请
    Video processing architecture definition by function graph methodology 失效
    视频处理架构通过功能图方法定义

    公开(公告)号：US20060143588A1

    公开(公告)日：2006-06-29

    申请号：US11105772

    申请日：2005-04-13

    申请人： Li Sha ,  Weimin Zeng

    发明人： Li Sha ,  Weimin Zeng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.

    摘要翻译： 公开了一种设计技术，其允许视频处理硬件设计者在设计过程的硬件架构设计阶段期间有效地采用视频处理标准（例如，H.264规范或其他此类标准）的要求。 该技术消除或以其他方式减少了设计过程的资源密集型实施和验证部分的昂贵的多次通过，并允许设计者对硬件架构设计进行更改，从而确保在实施阶段的验证。

    Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention
    10.
    发明授权
    Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention 失效
    处理单元具有交叉耦合的ALU /累加器和输入数据反馈结构，包括恒定发生器和旁路以减少内存争用

    公开(公告)号：US06996702B2

    公开(公告)日：2006-02-07

    申请号：US10209109

    申请日：2002-07-30

    申请人： Shuhua Xiang ,  Li Sha ,  Ping Zhu ,  Hongjun Yuan ,  Wei Ni

    发明人： Shuhua Xiang ,  Li Sha ,  Ping Zhu ,  Hongjun Yuan ,  Wei Ni

    IPC分类号： G06F9/34

    CPC分类号： G06F9/3867 ,  G06F7/57 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3885

    摘要： A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.

    摘要翻译： 处理系统包括算术逻辑单元（ALU）子系统，其允许与先前指令相关联的数据被保留以用于下一个指令或后续指令，而不必使用中间寄存器重新加载该值。 ALU子系统包括与一对蓄能器通信地交叉耦合的一对ALU。 处理系统还包括耦合到ALU子系统以与存储器争用预测一起使用的数据选择器。 数据选择器包括恒定发生器，其控制与旁路元件中的先前指令相关联的数据的存储，以及选择器，用于在数据总线元件的数据和存储在旁路元件中的数据之间进行选择。