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    Systems for executing load instructions that achieve sequential load consistency
    1.
    发明授权
    Systems for executing load instructions that achieve sequential load consistency 失效
    用于执行实现顺序负载一致性的加载指令的系统

    公开(公告)号：US07730290B2

    公开(公告)日：2010-06-01

    申请号：US12036992

    申请日：2008-02-25

    申请人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F9/383 ,  G06F12/0855

    摘要： A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

    摘要翻译： 公开了一种用于执行加载指令的方法。 加载指令的地址信息用于生成所需数据的地址，该地址用于搜索所需数据的高速缓冲存储器。 如果在高速缓冲存储器中找到所需的数据，则产生高速缓存命中信号。 地址的至少一部分用于在队列中搜索指定相同地址的先前加载指令。 如果找到指定相同地址的先前加载指令，则忽略缓存命中信号，并将加载指令存储在队列中。 还描述了加载/存储单元和实现该方法的处理器。

    Method and systems for executing load instructions that achieve sequential load consistency
    2.
    发明授权
    Method and systems for executing load instructions that achieve sequential load consistency 失效
    执行负载指令的方法和系统，以实现连续的负载一致性

    公开(公告)号：US07376816B2

    公开(公告)日：2008-05-20

    申请号：US10988310

    申请日：2004-11-12

    申请人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/383 ,  G06F12/0855

    摘要： A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

    摘要翻译： 公开了一种用于执行加载指令的方法。 加载指令的地址信息用于生成所需数据的地址，该地址用于搜索所需数据的高速缓冲存储器。 如果在高速缓冲存储器中找到所需的数据，则产生高速缓存命中信号。 地址的至少一部分用于在队列中搜索指定相同地址的先前加载指令。 如果找到指定相同地址的先前加载指令，则忽略缓存命中信号，并将加载指令存储在队列中。 还描述了加载/存储单元和实现该方法的处理器。

    SYSTEMS FOR EXECUTING LOAD INSTRUCTIONS THAT ACHIEVE SEQUENTIAL LOAD CONSISTENCY
    3.
    发明申请
    SYSTEMS FOR EXECUTING LOAD INSTRUCTIONS THAT ACHIEVE SEQUENTIAL LOAD CONSISTENCY 失效
    执行顺序负载一致的负载指令系统

    公开(公告)号：US20080148017A1

    公开(公告)日：2008-06-19

    申请号：US12036992

    申请日：2008-02-25

    申请人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F9/312

    CPC分类号： G06F9/383 ,  G06F12/0855

    摘要： A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

    摘要翻译： 公开了一种用于执行加载指令的方法。 加载指令的地址信息用于生成所需数据的地址，该地址用于搜索所需数据的高速缓冲存储器。 如果在高速缓冲存储器中找到所需的数据，则产生高速缓存命中信号。 地址的至少一部分用于在队列中搜索指定相同地址的先前加载指令。 如果找到指定相同地址的先前加载指令，则忽略缓存命中信号，并将加载指令存储在队列中。 还描述了加载/存储单元和实现该方法的处理器。

    Systems and methods for executing load instructions that avoid order violations
    4.
    发明授权
    Systems and methods for executing load instructions that avoid order violations 失效
    执行加载指令的系统和方法，以避免违规违规

    公开(公告)号：US07302527B2

    公开(公告)日：2007-11-27

    申请号：US10988284

    申请日：2004-11-12

    申请人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F12/00

    CPC分类号： G06F9/3851 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3834

    摘要： Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load and/or store instruction specifying the same address. If such a previous load/store instruction is found, the thread information is used to determine if the previous load/store instruction is from the same thread. If the previous load/store instruction is from the same thread, the cache hit signal is ignored, and the load instruction is stored in the queue. A load/store unit is also described.

    摘要翻译： 公开了执行加载指令的方法。 在一种方法中，接收加载指令和对应的线程信息。 加载指令的地址信息用于生成所需数据的地址，并且该地址用于搜索所需数据的高速缓冲存储器。 如果在高速缓冲存储器中找到所需的数据，则产生高速缓存命中信号。 地址的至少一部分用于搜索队列以获得指定相同地址的先前加载和/或存储指令。 如果找到这样的先前加载/存储指令，则使用线程信息来确定先前的加载/存储指令是否来自同一线程。 如果先前的加载/存储指令来自同一个线程，则忽略缓存命中信号，并将加载指令存储在队列中。 还描述了加载/存储单元。

    Method of load/store dependencies detection with dynamically changing address length
    7.
    发明授权
    Method of load/store dependencies detection with dynamically changing address length 失效
    使用动态变化的地址长度进行加载/存储依赖关系检测的方法

    公开(公告)号：US07464242B2

    公开(公告)日：2008-12-09

    申请号：US11050039

    申请日：2005-02-03

    申请人： Brian David Barrick ,  Dwain Alan Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Dwain Alan Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0623 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0802

    摘要： A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于通过动态地改变地址宽度进行比较来检测存储器系统中的加载/存储相关性。 必须将进入的加载/存储操作与流水线和队列中的操作进行比较，以避免地址冲突。 总的来说，本发明将缓存命中或高速缓存未命中输入引入到加载/存储依赖逻辑中。 如果进入加载操作是缓存命中，则使用四字边界地址值进行检测。 如果进入加载操作是高速缓存未命中，则使用高速缓存行边界地址值进行检测。 本发明增强了存储系统中LHS和LHR操作的性能。

    Method of updating cache state information where stores only read the cache state information upon entering the queue
    9.
    发明授权
    Method of updating cache state information where stores only read the cache state information upon entering the queue 失效
    更新高速缓存状态信息的方法，其中存储仅在进入队列时读取高速缓存状态信息

    公开(公告)号：US07302530B2

    公开(公告)日：2007-11-27

    申请号：US10897348

    申请日：2004-07-22

    申请人： Brian David Barrick ,  Dwain Alan Hicks ,  Takeki Osanai

    发明人： Brian David Barrick ,  Dwain Alan Hicks ,  Takeki Osanai

    IPC分类号： G06F12/08

    CPC分类号： G06F9/3834 ,  G06F12/0815 ,  G06F12/0855

    摘要： The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store/load queue. In this invention, store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. When the modification is an invalidate, the check tests that the two share the same physical addressable location. When the modification is a validate, the check tests that the two involve the same data cache line.

    摘要翻译： 本发明提供了一种在系统中更新用于存储事务的高速缓存状态信息的方法，其中存储事务仅在进入存储/加载队列的单元管道或存储部分时才读取高速缓存状态信息。 在本发明中，每当修改高速缓存行时检查单元管道和队列中的事务，并根据需要更新其缓存状态信息。 当修改无效时，检查测试两个共享相同的物理可寻址位置。 当修改是有效的，检查测试两个涉及相同的数据高速缓存行。

    Programmable data prefetch pacing
    10.
    发明授权
    Programmable data prefetch pacing 失效
    可编程数据预取起搏

    公开(公告)号：US06578130B2

    公开(公告)日：2003-06-10

    申请号：US09981880

    申请日：2001-10-18

    申请人： Brian David Barrick ,  Michael John Mayfield ,  Brian Patrick Hanley

    发明人： Brian David Barrick ,  Michael John Mayfield ,  Brian Patrick Hanley

    IPC分类号： G06F1200

    CPC分类号： G06F12/0897 ,  G06F12/0862

    摘要： A method and apparatus for prefetching data in computer systems that tracks the number of prefetches currently active and compares that number to a preset maximum number of allowable prefetches to determine if additional prefetches should currently be performed. By limiting the number of prefetches being performed at any given time, the use of system resources for prefetching can be controlled, and thus system performance can be optimized.

    摘要翻译： 一种用于在计算机系统中预取数据的方法和装置，其跟踪当前活动的预取数，并将该数量与预设的最大允许预取数量进行比较，以确定是否应当执行附加预取。 通过限制在任何给定时间执行的预取数量，可以控制用于预取的系统资源的使用，从而可以优化系统性能。