Programmable data prefetch pacing
    1.
    发明授权
    Programmable data prefetch pacing 失效
    可编程数据预取起搏

    公开(公告)号:US06578130B2

    公开(公告)日:2003-06-10

    申请号:US09981880

    申请日:2001-10-18

    IPC分类号: G06F1200

    CPC分类号: G06F12/0897 G06F12/0862

    摘要: A method and apparatus for prefetching data in computer systems that tracks the number of prefetches currently active and compares that number to a preset maximum number of allowable prefetches to determine if additional prefetches should currently be performed. By limiting the number of prefetches being performed at any given time, the use of system resources for prefetching can be controlled, and thus system performance can be optimized.

    摘要翻译: 一种用于在计算机系统中预取数据的方法和装置,其跟踪当前活动的预取数,并将该数量与预设的最大允许预取数量进行比较,以确定是否应当执行附加预取。 通过限制在任何给定时间执行的预取数量,可以控制用于预取的系统资源的使用,从而可以优化系统性能。

    Pseudo-LRU virtual counter for a locking cache
    2.
    发明授权
    Pseudo-LRU virtual counter for a locking cache 失效
    用于锁定缓存的伪LRU虚拟计数器

    公开(公告)号:US07516275B2

    公开(公告)日:2009-04-07

    申请号:US11380140

    申请日:2006-04-25

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    摘要: A computer implemented method and system for managing replacement of sets in a locked cache. A cache access by a program is performed, and a side of a binary tree pointed to by a base leaf is identified. A determination is made as to whether a number of accesses to the identified side of the binary tree equals a number of sets associated with the program on the identified side. The base leaf is changed to point to an opposite side of the binary tree if the number of accesses to the identified side equals the number of sets associated with the program on the identified side.

    摘要翻译: 用于管理锁定高速缓存中的集合的替换的计算机实现的方法和系统。 执行程序的高速缓存访​​问,并且识别由基本叶指向的二叉树的一侧。 确定对二叉树的所识别侧的访问次数是否等于与所识别侧上的程序相关联的集合的数量。 如果对所识别的边的访问次数等于与识别侧的程序相关联的集合的数目,则将基础叶改变为指向二叉树的相对侧。

    Apparatus for cache use history encoding and decoding including next lru and next mru and method therefor
    3.
    发明授权
    Apparatus for cache use history encoding and decoding including next lru and next mru and method therefor 失效
    用于缓存使用历史编码和解码的装置,包括下一个下一个mru及其方法

    公开(公告)号:US06338120B1

    公开(公告)日:2002-01-08

    申请号:US09259177

    申请日:1999-02-26

    IPC分类号: G06F1200

    摘要: An apparatus for encoding/decoding an associative cache set use history, and method therefor, is implemented. A five-bit signal is used to fully encode a four-way cache. A least recently used (LRU) set is encoded using a first bit pair, and a second bit pair encodes a most recently used (MRU) set. The sets having intermediate usage are encoded by a remaining single bit. The single bit has a first predetermined value when the sets having intermediate usage have an in-order relationship in accordance with a predetermined ordering of the cache sets. The single bit has a second predetermined value when the sets having intermediate usage have an out-of-order relationship.

    摘要翻译: 一种用于编码/解码关联高速缓存集使用历史的装置及其方法。 五位信号用于对四路缓存进行完全编码。 使用第一位对编码最近最少使用的(LRU)集合,并且第二位对对最近使用的(MRU)集合进行编码。 具有中间使用的集合由剩余的单个位编码。 当具有中间使用的集合根据高速缓存集的预定顺序具有顺序关系时,单个位具有第一预定值。 当具有中间使用的集合具有无序关系时,单个位具有第二预定值。

    Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system
    4.
    发明授权
    Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system 失效
    一种用于在数据处理系统内的四路高速缓冲存储器中实现伪最近最少使用(LRU)机制的方法

    公开(公告)号:US06240489B1

    公开(公告)日:2001-05-29

    申请号:US09256373

    申请日:1999-02-24

    IPC分类号: G06F1200

    CPC分类号: G06F12/125

    摘要: A method for implementing a pseudo least recent used mechanism in a four-way cache memory within a data processing system is disclosed. Within a four-way set associative cache memory, each congruence class contains four cache lines. Each congruence class within the cache memory is associated to a least recently used (LRU) field that has four bits. Each of four cache lines within the congruence class is then assigned with a respective set number. The set number of a cache line designated as a least recently used set among the four cache lines is stored in two bits of the LRU field. The set number of a cache line designated as a most recently used set among the four cache lines is stored in another two bits of the LRU field. In response to a determination that the set number of the least recently used set is higher than the set number of the most recently used set, one of the remaining two cache lines that has a higher set number is assigned to be a second least recently used set.

    摘要翻译: 公开了一种用于在数据处理系统内的四路高速缓冲存储器中实现伪近期使用机制的方法。 在四向组关联缓存内存中,每个同余类包含四个缓存行。 高速缓冲存储器内的每个同余类与具有四位的最近最少使用的(LRU)字段相关联。 然后在同余类中的四个缓存行中的每一个被分配相应的设定数。 在四个高速缓存行中指定为最近最少使用的集合的高速缓存行的设定数量被存储在LRU字段的两位中。 指定为四个高速缓存行中最近使用的集合的高速缓存行的设定数量被存储在LRU字段的另外两个位中。 响应于最近最少使用的集合的设置数量高于最近使用的集合的设定数量的确定,具有较高设置号码的剩余两条高速缓存行之一被分配为第二最近最近使用的 组。