Pseudo-LRU virtual counter for a locking cache
    1.
    发明授权
    Pseudo-LRU virtual counter for a locking cache 失效
    用于锁定缓存的伪LRU虚拟计数器

    公开(公告)号:US07516275B2

    公开(公告)日:2009-04-07

    申请号:US11380140

    申请日:2006-04-25

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    摘要: A computer implemented method and system for managing replacement of sets in a locked cache. A cache access by a program is performed, and a side of a binary tree pointed to by a base leaf is identified. A determination is made as to whether a number of accesses to the identified side of the binary tree equals a number of sets associated with the program on the identified side. The base leaf is changed to point to an opposite side of the binary tree if the number of accesses to the identified side equals the number of sets associated with the program on the identified side.

    摘要翻译: 用于管理锁定高速缓存中的集合的替换的计算机实现的方法和系统。 执行程序的高速缓存访​​问,并且识别由基本叶指向的二叉树的一侧。 确定对二叉树的所识别侧的访问次数是否等于与所识别侧上的程序相关联的集合的数量。 如果对所识别的边的访问次数等于与识别侧的程序相关联的集合的数目,则将基础叶改变为指向二叉树的相对侧。

    System and method for reducing store latency in symmetrical multiprocessor systems
    2.
    发明授权
    System and method for reducing store latency in symmetrical multiprocessor systems 有权
    用于在对称多处理器系统中减少存储延迟的系统和方法

    公开(公告)号:US07519780B2

    公开(公告)日:2009-04-14

    申请号:US11556346

    申请日:2006-11-03

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0817

    摘要: A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.

    摘要翻译: 提供了一种用于在对称多处理器系统中减少存储延迟的系统和方法。 提供巴士代理,监控反映的所有权请求(Dclaims),以确定反映的Dclaim是否是自己的Dclaim。 如果是这样,总线代理确定它是所有权请求的获胜者,并且可以使用其关联的本地高速缓存立即执行数据修改。 如果总线代理确定反映的Dclaim与其自己的Dclaim不匹配,则它确定它是所有权请求的输家,并使其本地缓存中的相应缓存行无效。 失败者总线代理可以随后发送读取有意图修改请求以从另一个高速缓存获取数据并将其放入其自己的高速缓存中进行修改。 这些操作在不需要杀死请求的情况下执行,而不必执行失败的所有权请求的重试。

    System and Method for Reducing Store Latency in Symmetrical Multiprocessor Systems
    3.
    发明申请
    System and Method for Reducing Store Latency in Symmetrical Multiprocessor Systems 有权
    减少对称多处理器系统中存储延迟的系统和方法

    公开(公告)号:US20080109585A1

    公开(公告)日:2008-05-08

    申请号:US11556346

    申请日:2006-11-03

    IPC分类号: G06F13/364

    CPC分类号: G06F12/0817

    摘要: A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.

    摘要翻译: 提供了一种用于在对称多处理器系统中减少存储延迟的系统和方法。 提供巴士代理,监控反映的所有权请求(Dclaims),以确定反映的Dclaim是否是自己的Dclaim。 如果是这样,总线代理确定它是所有权请求的获胜者,并且可以使用其关联的本地高速缓存立即执行数据修改。 如果总线代理确定反映的Dclaim与其自己的Dclaim不匹配,则它确定它是所有权请求的输家,并使其本地缓存中的相应缓存行无效。 失败者总线代理可以随后发送读取有意图修改请求以从另一个高速缓存获取数据并将其放入其自己的高速缓存中进行修改。 这些操作在不需要杀死请求的情况下执行,而不必执行失败的所有权请求的重试。

    Implementation of a pseudo-LRU algorithm in a partitioned cache
    4.
    发明授权
    Implementation of a pseudo-LRU algorithm in a partitioned cache 失效
    在分区高速缓存中实现伪LRU算法

    公开(公告)号:US07069390B2

    公开(公告)日:2006-06-27

    申请号:US10655401

    申请日:2003-09-04

    IPC分类号: G06F12/12

    摘要: The present invention provides for a plurality of partitioned ways of an associative cache. A pseudo-least recently used binary tree is provided, as is a way partition binary tree, and signals are derived from the way partition binary tree as a function of a mapped partition. Signals from the way partition binary tree and the pseudo-least recently used binary tree are combined. A cache line replacement signal is employable to select one way of a partition as a function of the pseudo-least recently used binary tree and the signals derived from the way partition binary tree.

    摘要翻译: 本发明提供了关联高速缓存的多个分割方式。 提供了一种伪最近最少使用的二叉树,也是分配二叉树的一种方式,并且信号是从分配二叉树的方式导出的,作为映射分区的函数。 从分区二叉树和伪最小最近使用的二进制树的方式组合信号。 高速缓存行替换信号可用于根据伪最近最少使用的二叉树和从分区二叉树方式导出的信号来选择分区的一种方式。