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公开(公告)号：US06940437B2
公开(公告)日：2005-09-06
申请号：US10699466
申请日：2003-10-31
CPC分类号： H03M7/3011 , H03M7/3026 , H03M7/3037
摘要： A method of operating a delta-sigma modulator by providing a variable-level quantizer, which selectively enables an additional quantizer level(s) during a ramp up sequence of the modulator. The additional quantizer level(s) is/are disabled during normal operation. The quantizer truncates a summer output and selectively enables the additional quantizer levels by clipping the truncated sum within a first range of quantizer levels during the ramp up sequence and within a second range of quantizer levels during normal operation in which there are more quantizer levels in the first range than in the second range. The quantizer preferably enables at least two additional quantizer levels at a low end of the quantizer range. For example, the range of quantizer levels for normal operation of the modulator can be from −6 to +6, while the range of quantizer levels for ramp up operation of the modulator can be from −8 to +7.
摘要翻译： 一种通过提供可变电平量化器来操作Δ-Σ调制器的方法，该可变电平量化器在调制器的斜坡上升序列期间选择性地启用附加的量化器电平。 额外的量化器电平在正常操作期间被禁用。 量化器截断加法器输出，并且通过在斜坡上升序列期间在量化器电平的第一范围内以及在正常操作的第二范围内的量化器电平的第二范围内削减截断的和来选择性地启用附加的量化器电平，其中在 第一范围比第二范围。 量化器优选地在量化器范围的低端使能至少两个附加的量化器电平。 例如，调制器的正常操作的量化器电平的范围可以是从-6到+6，而调制器的上升操作的量化器电平的范围可以是从-8到+7。
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2.发明授权Method and apparatus for reducing noise in a digital-to-analog converter (DAC) having a chopper output stage 有权具有斩波输出级的数/模转换器（DAC）中的噪声降低方法和装置公开(公告)号：US07277035B1
公开(公告)日：2007-10-02
申请号：US11428108
申请日：2006-06-30
申请人： Zhong You , Brian David Trotter , John L. Melanson
发明人： Zhong You , Brian David Trotter , John L. Melanson
IPC分类号： H03M1/66
摘要： A method and apparatus for reducing noise in a digital-to-analog converter (DAC) having a chopper amplifier output stage provides improved DAC performance. A switched-current output provided from a digital filter is coupled to the input of a chopper amplifier. The current switches are non-uniform, so that extra zeros are provided at the chopping frequency of the chopping amplifier, thereby reducing noise that would otherwise be aliased in-band at the output of the chopper amplifier. The current switches may include a first set of half-magnitude switches followed by a set of full-magnitude switches and finally by another set of half-magnitude switches having a size equal to that of the first set.
摘要翻译： 用于降低具有斩波放大器输出级的数模转换器（DAC）中的噪声的方法和装置提供改进的DAC性能。 从数字滤波器提供的开关电流输出耦合到斩波放大器的输入端。 电流开关是不均匀的，因此在斩波放大器的斩波频率处提供额外的零，从而减少否则将在斩波放大器的输出处带内的混叠噪声。 电流开关可以包括第一组半幅度开关，随后是一组全幅度开关，最后还包括具有等于第一组尺寸的另一组半幅度开关。
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3.发明授权Methods for output edge-balancing in pulse width modulation systems and data converters using the same 有权用于脉冲宽度调制系统中输出边沿平衡的方法和使用其的数据转换器公开(公告)号：US06965335B1
公开(公告)日：2005-11-15
申请号：US10765443
申请日：2004-01-27
CPC分类号： H03M7/3006 , H02M2003/1586 , H03M3/506 , H03M7/3015 , H03M7/3026 , H03M7/3037
摘要： A method of performing digital to analog conversion includes generating a pulse width modulated data stream and another pulse width modulated data stream, encoding patterns of the pulse width modulated data stream selected to minimize distortion in the another pulse width modulated stream caused by edges in the pulse width modulated data stream. The pulse width modulated data stream and the another pulse width modulated data stream are converted into an analog signal and another analog signal converting in corresponding digital to analog conversion elements and the analog signal and the another analog signal are summed to generate an analog output signal.
摘要翻译： 执行数模转换的方法包括生成脉冲宽度调制数据流和另一个脉宽调制数据流，编码脉宽调制数据流的模式，以选择最小化由脉冲中的边缘引起的另一个脉宽调制流中的失真 宽度调制数据流。 将脉冲宽度调制数据流和另一个脉冲宽度调制数据流转换成模拟信号，并在相应的数/模转换元件中转换另一个模拟信号，并将模拟信号和另一模拟信号相加以产生模拟输出信号。
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4.发明授权Constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus 有权恒边缘三进制输出连续边缘调制器（CEM）方法和装置公开(公告)号：US07327295B1
公开(公告)日：2008-02-05
申请号：US11343027
申请日：2006-01-30
IPC分类号： H03M3/00
摘要： A constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus provides improved dynamic range in a noise-shaped CEM ternary pulse generator. A noise shaper shapes an input signal that is supplied to a pair of CEMs through a mismatch shaper or other code splitter that assigns unequal pulse width portions (the extra count in odd counts) between the pair of CEMs. The range of pulse width out of the CEMs can then be allowed to extend to the full sample period for one or possibly both of the CEMs in a given cycle. A control circuit overrides the mismatch shaper's assignment of the unequal pulse width portions when a previous pulse period yielded no transition from a given CEM, so that the given CEM is guaranteed to have a transition in the current pulse period.
摘要翻译： 恒定边缘速率三进制输出连续边缘调制器（CEM）方法和装置在噪声形状的CEM三元脉冲发生器中提供改进的动态范围。 噪声整形器通过错配整形器或其他代码分离器来形成输入信号，该输入信号通过在一对CEM之间分配不相等的脉冲宽度部分（奇数的额外计数）而被提供给一对CEM。 然后可以允许CEM中的脉冲宽度范围延伸到给定周期中的一个或可能两个CEM的完整采样周期。 当先前的脉冲周期不产生从给定的CEM的转变时，控制电路覆盖不匹配整形器对不等的脉冲宽度部分的分配，使得给定的CEM被保证在当前脉冲周期内具有转变。
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5.发明授权公开(公告)号：US07167118B1
公开(公告)日：2007-01-23
申请号：US11297016
申请日：2005-12-08
IPC分类号： H03M3/00
CPC分类号： H03M3/506 , H03M7/3026 , H03M7/3037
摘要： A centered-pulse consecutive edge modulation (CEM) method and apparatus provides a pulse output that advantageously exploits the full edge update rate of the CEM while providing substantially centered pulses. The method and apparatus also operate without substantial delay in the input control path. The apparatus includes a delta-sigma noise shaping modulator followed by a CEM that receives an output of the delta-sigma modulator quantizer. A non-linear correction signal is applied with polarity alternating at each edge and is applied to the quantizer input or is designed into the quantizer transfer function. The non-linear correction signal compensates for the noise-shaping modulator output such that the expected rising edge and falling edge widths of the CEM output pulses are substantially equal with respect to a DC input to the delta-sigma modulator.
摘要翻译： 中心脉冲连续边缘调制（CEM）方法和装置提供脉冲输出，其有利地利用CEM的全边缘更新速率，同时提供基本上居中的脉冲。 该方法和装置也在输入控制路径中没有实质延迟的情况下工作。 该装置包括后跟有CEM的Δ-Σ噪声整形调制器，其接收Δ-Σ调制器量化器的输出。 在每个边缘处以极性交替施加非线性校正信号，并施加到量化器输入或被设计成量化器传递函数。 非线性校正信号补偿噪声整形调制器输出，使得CEM输出脉冲的预期上升沿和下降沿宽度相对于Δ-Σ调制器的DC输入基本相等。
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公开(公告)号：US06956919B2
公开(公告)日：2005-10-18
申请号：US10292320
申请日：2002-11-12
IPC分类号： G11B20060101 , G11B3/00 , G11B20/10 , G11B20/14 , H03K9/00 , H04L7/00 , H04L25/45 , H04L27/00 , H04L27/06
CPC分类号： H04L25/45 , G11B20/10527 , G11B20/1403
摘要： Methods and apparatus are provided for receiving DSD data in phase modulation mode using a single clock signal. Either the bit clock or phase signal may be used.
摘要翻译： 提供了使用单个时钟信号在相位调制模式下接收DSD数据的方法和装置。 可以使用位时钟或相位信号。
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7.发明授权Data converters with ternary pulse width modulation output stages and methods and systems using the same 有权具有三进制脉宽调制输出级的数据转换器及使用其的方法和系统公开(公告)号：US06885330B2
公开(公告)日：2005-04-26
申请号：US10656749
申请日：2003-09-05
CPC分类号： H03M3/506
摘要： A pulse width modulator includes at least one input for receiving an input signal and pulse width modulation circuitry for generating a pulse width modulated stream and another pulse width modulated stream. The pulse width modulated stream and the another pulse width modulated stream are nominally out of phase and together represent the received input signal. A summer sums the pulse width modulated stream and the another pulse width modulated stream to generate an analog output signal.
摘要翻译： 脉冲宽度调制器包括用于接收输入信号的至少一个输入端和用于产生脉冲宽度调制流和另一脉冲宽度调制流的脉宽调制电路。 脉冲宽度调制流和另一脉冲宽度调制流标称上是异相的，并且一起表示所接收的输入信号。 夏季将脉冲宽度调制流和另一脉冲宽度调制流相加以产生模拟输出信号。
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