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    Circuit systems and methods for multirate digital-to-analog amplifier systems
    1.
    发明授权
    Circuit systems and methods for multirate digital-to-analog amplifier systems 有权
    多速率数模转换放大器系统的电路系统和方法

    公开(公告)号：US06462690B1

    公开(公告)日：2002-10-08

    申请号：US09825445

    申请日：2001-04-02

    Applicant: Johann Guy Gaboriau ,  Xiaofan Fei ,  Evan Logan Marchman ,  Jason Powell Rhode

    Inventor： Johann Guy Gaboriau ,  Xiaofan Fei ,  Evan Logan Marchman ,  Jason Powell Rhode

    IPC: H03M166

    CPC classification number: H03M3/502

    Abstract: A multirate digital-to-analog amplifier system is disclosed. An interpolator is configured to interpolate digital values between samples of a digital signal from a digital signal source, in which the digital signal has a first sample rate. An output signal from the interpolator has a second, predetermined sample rate, which is independent of the first sample rate, of the digital signal. An amplifier is configured to amplify a digital signal having the second sample rate in response to the output signal of the interpolator.

    Abstract translation: 公开了一种多速率数模转换放大器系统。 内插器被配置为在来自数字信号源的数字信号的采样之间内插数字值，其中数字信号具有第一采样率。 来自内插器的输出信号具有与数字信号的第一采样速率无关的第二预定采样速率。 放大器被配置为响应于内插器的输出信号放大具有第二采样率的数字信号。

    One line data format for audio analog-to-digital converters
    4.
    发明授权
    One line data format for audio analog-to-digital converters 有权
    音频模数转换器的一行数据格式

    公开(公告)号：US06657574B1

    公开(公告)日：2003-12-02

    申请号：US10314555

    申请日：2002-12-09

    Applicant: Jason Powell Rhode

    Inventor： Jason Powell Rhode

    IPC: H03M112

    CPC classification number: H03M3/466 ,  H03M1/1205

    Abstract: An analog-to-digital converter is provided for converting multiple analog inputs into corresponding digital values. An output interface circuit uses differential signaling to reduce noise and interference induced in the analog portions of the analog-to-digital converter.

    Abstract translation: 提供了一个模拟 - 数字转换器，用于将多个模拟输入转换为相应的数字值。 输出接口电路使用差分信令来减少在模数转换器的模拟部分中引起的噪声和干扰。

    Data conversion circuits and methods with input clock signal frequency detection and master mode output clock signal generation
    8.
    发明授权
    Data conversion circuits and methods with input clock signal frequency detection and master mode output clock signal generation 有权
    数据转换电路和方法具有输入时钟信号频率检测和主模式输出时钟信号的产生

    公开(公告)号：US06667704B1

    公开(公告)日：2003-12-23

    申请号：US10281715

    申请日：2002-10-28

    Applicant: Trenton John Grale ,  Jason Powell Rhode ,  Karl Thompson

    Inventor： Trenton John Grale ,  Jason Powell Rhode ,  Karl Thompson

    IPC: H03M100

    CPC classification number: H04J3/0685 ,  H04J3/0688

    Abstract: A data converter includes first and second input signal paths receiving an input signal having an input frequency, the first input signal path dividing the input frequency by a first divisor and the second input signal path dividing the input frequency by a second divisor, the second divisor being greater than the first divisor. A selector selects between an output of the first input signal path and an output from the second input signal path in response to a state of a control signal. Control circuitry monitors a selector output signal frequency and a current state of the control signal and selectively resets the state of the control signal to set the selector output frequency to a desired frequency.

    Abstract translation: 数据转换器包括接收具有输入频率的输入信号的第一和第二输入信号路径，第一输入信号路径将输入频率除以第一除数，第二输入信号路径将输入频率除以第二除数，第二除数 大于第一个除数。 选择器响应于控制信号的状态，在第一输入信号路径的输出和来自第二输入信号路径的输出之间进行选择。 控制电路监视选择器输出信号频率和控制信号的当前状态，并选择性地复位控制信号的状态，以将选择器输出频率设置到期望的频率。

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