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公开(公告)号：US06940437B2
公开(公告)日：2005-09-06
申请号：US10699466
申请日：2003-10-31
CPC分类号： H03M7/3011 , H03M7/3026 , H03M7/3037
摘要： A method of operating a delta-sigma modulator by providing a variable-level quantizer, which selectively enables an additional quantizer level(s) during a ramp up sequence of the modulator. The additional quantizer level(s) is/are disabled during normal operation. The quantizer truncates a summer output and selectively enables the additional quantizer levels by clipping the truncated sum within a first range of quantizer levels during the ramp up sequence and within a second range of quantizer levels during normal operation in which there are more quantizer levels in the first range than in the second range. The quantizer preferably enables at least two additional quantizer levels at a low end of the quantizer range. For example, the range of quantizer levels for normal operation of the modulator can be from −6 to +6, while the range of quantizer levels for ramp up operation of the modulator can be from −8 to +7.
摘要翻译： 一种通过提供可变电平量化器来操作Δ-Σ调制器的方法，该可变电平量化器在调制器的斜坡上升序列期间选择性地启用附加的量化器电平。 额外的量化器电平在正常操作期间被禁用。 量化器截断加法器输出，并且通过在斜坡上升序列期间在量化器电平的第一范围内以及在正常操作的第二范围内的量化器电平的第二范围内削减截断的和来选择性地启用附加的量化器电平，其中在 第一范围比第二范围。 量化器优选地在量化器范围的低端使能至少两个附加的量化器电平。 例如，调制器的正常操作的量化器电平的范围可以是从-6到+6，而调制器的上升操作的量化器电平的范围可以是从-8到+7。
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2.发明授权Systems and methods for clock mode determination utilizing divide ratio testing 有权使用分频比测试的时钟模式确定的系统和方法公开(公告)号：US07286069B1
公开(公告)日：2007-10-23
申请号：US11136215
申请日：2005-05-24
IPC分类号： H03M1/00
CPC分类号： G06F1/06
摘要： A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal. In additional embodiments, the mapping system gives preference to natural number divide ratios during mode mapping.
摘要翻译： 用于确定数据转换器操作模式的系统包括用于测量主时钟信号的主时钟频率和数据时钟信号的频率与主时钟频率之间的频率比的测量电路和用于映射频率测量的映射系统 与数据转换器的操作模式的比率。 映射系统产生一组候选分频比，用于划分主时钟频率以产生内部时钟信号的相应内部主时钟频率，并确定产生支持的内部主时钟频率的最低分频比。 在替代实施例中，映射系统通过将数据时钟与主时钟频率比除以数据时钟与数据时钟频率与内部频率之间的内部时钟频率比来确定数据转换器的滤波器所需的分频比 时钟信号。 在另外的实施例中，映射系统在模式映射期间优先考虑自然数分配比。
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3.发明授权Noise management method and circuits suitable for utilization in circuits and systems having a switched data port 有权适用于具有切换数据端口的电路和系统中的噪声管理方法和电路公开(公告)号：US07248186B1
公开(公告)日：2007-07-24
申请号：US11086942
申请日：2005-03-22
申请人： Bruce Eliot Duewer
发明人： Bruce Eliot Duewer
IPC分类号： H03M7/00
CPC分类号： H04L25/08 , G06F3/16 , H04L25/028
摘要： A method of reducing noise in a system utilizing a serial port includes generating a data word having a selected number of bits and ensuring that a last bit of the data word corresponds to a first bit of a next data word. The data word is output through the serial port and the next data word switched for output through the serial port in response to an event.
摘要翻译： 使用串行端口的减少系统噪声的方法包括产生具有所选位数的数据字，并确保数据字的最后一位对应于下一个数据字的第一位。 数据字通过串行端口输出，下一个数据字通过串行端口切换以响应事件。
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公开(公告)号：US07379834B1
公开(公告)日：2008-05-27
申请号：US11135682
申请日：2005-05-24
CPC分类号： H04J3/0685 , G11B20/10222 , G11B20/14 , H03L7/00
摘要： A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal, the master clock frequency measurement biased by a past operating mode selection, and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In an additional embodiment, the measurement circuitry biases the master clock frequency measurement based on a past master clock frequency measurement.
摘要翻译： 一种用于确定数据转换器操作模式的系统包括测量电路，其可操作以测量主时钟信号的主时钟频率，主时钟频率测量由过去操作模式选择偏置，并且可操作以测量频率之间的频率比 数据时钟信号和主时钟频率。 映射系统将主时钟频率和频率比的测量结果映射到数据转换器的操作模式。 在另外的实施例中，测量电路基于过去的主时钟频率测量来偏置主时钟频率测量。
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公开(公告)号：US07376915B1
公开(公告)日：2008-05-20
申请号：US10960258
申请日：2004-10-07
IPC分类号： G06F17/50
CPC分类号： G01R31/318536
摘要： A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.
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6.发明授权Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same 有权在集成电路中形成区域有效的扫描链的方法以及体现其的集成电路公开(公告)号：US07971170B2
公开(公告)日：2011-06-28
申请号：US12082180
申请日：2008-04-09
CPC分类号： G01R31/318536
摘要： A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.
摘要翻译： 形成用于测试集成电路的扫描链的方法包括在集成电路设计中检查寄存器元件的互连。 识别寄存器元件段，其包括具有输出的源寄存器元件和具有直接耦合到源寄存器元件的输出的输入的目的地寄存器元件。 该段被选择性地耦合到另一个扫描寄存器元件以形成扫描链的一部分。
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7.发明授权公开(公告)号：US07400284B1
公开(公告)日：2008-07-15
申请号：US10811715
申请日：2004-03-29
IPC分类号： H03M1/66
CPC分类号： H03M1/0614
摘要： A circuit including a first element sampling noise from and discharging noise to a signal line in response to an input signal transitioning on selected edges of a clock signal. A second element samples noise from and discharges noise to the signal line in response to another input signal transitioning on other edges of the clock signal differing from the selected edges of the clock signal such that noise coupled into substrate and supply are independent of the input signal.
摘要翻译： 一种包括第一元件的电路，其响应于在时钟信号的选定边沿上的输入信号转换，从噪声和对信号线的噪声进行采样。 响应于另一个输入信号在与时钟信号的选定边沿不同的时钟信号的其他边沿上转换的另一个输入信号，噪声对噪声进行采样，并将噪声放大到信号线，使得耦合到衬底和电源中的噪声与输入信号无关 。
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8.发明授权Methods and circuit for suppressing transients in an output driver and data conversion systems using the same 有权用于抑制输出驱动器和使用其的数据转换系统中的瞬变的方法和电路公开(公告)号：US07068200B1
公开(公告)日：2006-06-27
申请号：US10868329
申请日：2004-06-15
IPC分类号： H03M1/66
CPC分类号： H03M1/0881 , H03M1/66
摘要： A driver circuit with power-down transient suppression includes an amplifier for driving a load coupled to an output of the amplifier, a ramp-down voltage generator having a capacitor and a resistor for generating a ramp-down voltage during power-down of the amplifier, and a differential transistor pair responsive to the ramp-down voltage for pulling-down current at the output of the amplifier during power-down of the amplifier.
摘要翻译： 具有掉电瞬变抑制的驱动器电路包括用于驱动耦合到放大器的输出的负载的放大器，具有电容器的降压电压发生器和用于在放大器掉电期间产生斜坡下降电压的电阻器 以及在放大器断电期间响应于用于在放大器的输出处的下拉电流的降压电压的差分晶体管对。
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9.发明授权Systems and methods for clock mode determination utilizing explicit formulae and lookup tables 有权使用显式公式和查找表进行时钟模式确定的系统和方法公开(公告)号：US07057539B1
公开(公告)日：2006-06-06
申请号：US11136059
申请日：2005-05-24
IPC分类号： H03M1/00
CPC分类号： G01R23/005
摘要： A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal and measure a frequency ratio between a data clock frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing an explicit formula. In a further embodiment, the mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing a lookup table. In an additional embodiment, the mapping system tests an available set of operating modes, independent of any previous tests, to determine a suitable operating mode for the data converter.
摘要翻译： 一种用于确定数据转换器操作模式的系统包括可操作以测量主时钟信号的主时钟频率并测量数据时钟信号的数据时钟频率与主时钟频率之间的频率比的测量电路。 映射系统使用显式公式将主时钟频率和频率比的测量值映射到数据转换器的操作模式。 在另一实施例中，映射系统使用查找表将主时钟频率和频率比的测量值映射到数据转换器的操作模式。 在另外的实施例中，映射系统独立于任何先前的测试来测试可用的一组操作模式，以确定数据转换器的合适的操作模式。
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10.发明授权Systems and methods for clock mode determination utilizing a fixed-frequency reference signal 有权使用固定频率参考信号的时钟模式确定的系统和方法公开(公告)号：US07049988B1
公开(公告)日：2006-05-23
申请号：US11136060
申请日：2005-05-24
IPC分类号： H03M1/00
CPC分类号： G11B20/10222 , G11B20/10009
摘要： A system for determining a data converter operating mode including measurement circuitry operable to measure a master clock frequency by comparing a frequency of a master clock signal and a frequency of a fixed frequency clock signal and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In one particular embodiment, the fixed frequency clock signal is provided by an oscillator. In a further embodiment, the master clock signal is generated by multiplying the frequency of another clock signal.
摘要翻译： 一种用于确定数据转换器操作模式的系统，包括测量电路，可操作以通过比较主时钟信号的频率和固定频率时钟信号的频率来测量主时钟频率，并可操作以测量数据频率之间的频率比 时钟信号和主时钟频率。 映射系统将主时钟频率和频率比的测量结果映射到数据转换器的操作模式。 在一个具体实施例中，固定频率时钟信号由振荡器提供。 在另一实施例中，主时钟信号是通过将另一个时钟信号的频率相乘而产生的。
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