公开(公告)号：US20050257036A1

公开(公告)日：2005-11-17

申请号：US10844300

申请日：2004-05-12

申请人： Brian Prasky ,  Moinuddin Khalil Qureshi

发明人： Brian Prasky ,  Moinuddin Khalil Qureshi

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3848

摘要： Disclosed is a method and apparatus providing the ability to create a multi-level prediction algorithm where branch predictions beyond the first level of prediction are maintained at a secondary level because the prior level was unsuccessfully able to highly predict accurate the direction of the stated branch. A secondary level is smaller in size than the upper level through selected filtering thereby enabling high prediction accuracy of branches while minimizing the amount of hardware to perform stated predictions.

摘要翻译： 公开了一种提供创建多级预测算法的能力的方法和装置，其中超过第一预测级别的分支预测保持在次级级别，因为先前级别不能高精度地预测所述分支的方向。 通过所选择的滤波，次级电平的尺寸小于上电平，从而能够实现分支的高预测精度，同时最小化执行所述预测的硬件量。

公开(公告)号：US20050204120A1

公开(公告)日：2005-09-15

申请号：US10796426

申请日：2004-03-09

申请人： Brian Prasky ,  Thomas Puzak ,  Allan Hartstein

发明人： Brian Prasky ,  Thomas Puzak ,  Allan Hartstein

IPC分类号： G06F9/00 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/325 ,  G06F9/381

摘要： Disclosed is a method and apparatus providing the capability to supplement a branch target buffer (BTB) with a recent entry queue. A recent entry queue prevents unnecessary removal of valuable BTB data of multiple entries for another entry. Additional, the recent entry queue detects when the latency of the BTB's startup latency is preventing it from asynchronous aiding the microprocessor pipeline as designed for and thereby can delay the pipeline in the required situations such that the BTB latency on startup can be overcome. Finally, the recent entry queue provides a quick access to BTB entries that are accessed in a tight loop pattern where the throughput of the standalone BTB is unable to track the throughput of the microprocessor execution pipeline. Through the usage of the recent entry queue, the modified BTB is capable of processing information at the rate of the execution pipeline thereby accelerating the execution pipeline.

摘要翻译： 公开了一种提供补充具有最近进入队列的分支目标缓冲器（BTB）的能力的方法和装置。 最近的入口队列可以防止不必要地删除另外一个条目的多个条目的有价值的BTB数据。 另外，最近的进入队列检测到BTB的启动延迟的延迟何时阻止它异步协助微处理器管道设计，从而可以在所需情况下延迟流水线，从而可以克服启动时的BTB延迟。 最后，最近的入口队列可以快速访问以严格环路模式访问的BTB条目，其中独立BTB的吞吐量无法跟踪微处理器执行管道的吞吐量。 通过使用最近的进入队列，修改后的BTB能够以执行流水线的速度处理信息，从而加速执行流水线。

公开(公告)号：US20060047913A1

公开(公告)日：2006-03-02

申请号：US10926478

申请日：2004-08-26

申请人： Linda Bigelow ,  Richard Bohn ,  Brian Prasky ,  Charles Vitu

发明人： Linda Bigelow ,  Richard Bohn ,  Brian Prasky ,  Charles Vitu

IPC分类号： G06F12/00

CPC分类号： G06F9/383 ,  G06F9/3832 ,  G06F9/3861

摘要： A method providing a microprocessor with the ability to predict data cache content based on the instruction address of an instruction which is accessing the data cache allows the reduction of address generation interlocking scenarios with the ability to self-correct should the data cache content prediction be incorrect. Content prediction accuracy is kept high through the use of multiple filters. One filter allows predictions to be only used in scenarios where address generation interlock scenarios are present. A second filter allows predictions to be made only when patterns are detected which suggest a prediction will be correct. The third and final filter further improves prediction coverage by detecting patterns of correct potential predictions and utilizing them in the future when they would otherwise be ignored by the basic prediction mechanism.

摘要翻译： 一种使微处理器能够基于正在访问数据高速缓存的指令的指令地址来预测数据高速缓存内容的方法允许如果数据高速缓存内容预测不正确，则能够减少地址生成互锁场景，具有自校正能力 。 通过使用多个滤波器，内容预测精度保持较高。 一个过滤器允许预测仅在存在地址生成互锁方案的情况下使用。 第二个滤波器只有在检测到模式时才能进行预测，这表明预测将是正确的。 第三和最后的滤波器通过检测正确的潜在预测的模式进一步提高预测覆盖范围，并且在将来会被基本预测机制忽略的情况下将来利用它们。

公开(公告)号：US20050120193A1

公开(公告)日：2005-06-02

申请号：US10724815

申请日：2003-12-01

申请人： Philip Emma ,  Allan Hartstein ,  Brian Prasky ,  Thomas Puzak ,  Moinuddin Ahmed Qureshi ,  Vijayalakshmi Srinivasan

发明人： Philip Emma ,  Allan Hartstein ,  Brian Prasky ,  Thomas Puzak ,  Moinuddin Ahmed Qureshi ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3806

摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.

摘要翻译： 存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。 基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。 第二个元结构与第一个元结构分层关联。 第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。 提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。

公开(公告)号：US20050257035A1

公开(公告)日：2005-11-17

申请号：US10844299

申请日：2004-05-12

申请人： Brian Prasky ,  John Liptay

发明人： Brian Prasky ,  John Liptay

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3808 ,  G06F9/3806

摘要： A method and apparatus for providing the capability to create a dynamic based buffer structure that takes an instruction addresses organized instruction cache and through the interaction of an asynchronous branch target buffer (BTB) and branch history table (BHT) forms a series of instructions that resembles a trace cache in the buffer structure. By allowing the dynamic creation of a predicted code sequence trace in the buffer structure, based on the past behavior of the instruction code, the usage of fetching is utilized and the instruction cache makes optimal use of area while reducing latency penalties associated with taken branches and branches which are predicted in the improper direction.

摘要翻译： 一种用于提供创建基于动态的缓冲器结构的能力的方法和装置，其采用指令地址组织的指令高速缓存，并且通过异步分支目标缓冲器（BTB）和分支历史表（BHT）的交互形成一系列类似于 缓冲区结构中的跟踪缓存。 通过允许在缓冲器结构中动态创建预测的代码序列跟踪，基于指令代码的过去行为，使用提取的使用，并且指令高速缓存能够最佳地利用区域，同时减少与所采用的分支相关联的延迟处罚， 在不正确的方向预测的分支。

公开(公告)号：US20080046703A1

公开(公告)日：2008-02-21

申请号：US11923902

申请日：2007-10-25

申请人： Philip Emma ,  Allan Hartstein ,  Brian Prasky ,  Thomas Puzak ,  Moinuddin Ahmed Qureshi ,  Vijayalakshmi Srinivasan

发明人： Philip Emma ,  Allan Hartstein ,  Brian Prasky ,  Thomas Puzak ,  Moinuddin Ahmed Qureshi ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/00

CPC分类号： G06F9/3806

摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.

摘要翻译： 存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。 基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。 第二个元结构与第一个元结构分层关联。 第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。 提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。

公开(公告)号：US20060095678A1

公开(公告)日：2006-05-04

申请号：US10926481

申请日：2004-08-26

申请人： Linda Bigelow ,  Richard Bohn ,  Brian Prasky ,  Charles Vitu

发明人： Linda Bigelow ,  Richard Bohn ,  Brian Prasky ,  Charles Vitu

IPC分类号： G06F12/14

CPC分类号： G06F12/0875 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3861

摘要： Disclosed is a method and apparatus providing a microprocessor the ability to reuse data cache content fetched during runahead execution. Said data is stored and later retrieved based upon the instruction address of an instruction which is accessing the data cache. The reuse mechanism allows the reduction of address generation interlocking scenarios with the ability to self-correct should the stored values be incorrect due to subtleties in the architected state of memory in multiprocessor systems.

摘要翻译： 公开了一种为微处理器提供在跑步执行期间获取的数据高速缓存内容的能力的方法和装置。 所述数据根据正在访问数据高速缓存的指令的指令地址进行存储和稍后检索。 如果多处理器系统中存储器的架构状态微妙，存储值将不正确，则重新使用机制允许减少地址生成互锁场景的自我修正能力。

公开(公告)号：US20050216713A1

公开(公告)日：2005-09-29

申请号：US10809749

申请日：2004-03-25

申请人： Brian Prasky ,  Mark Check ,  Bruce Giamei ,  Timothy Slegel

发明人： Brian Prasky ,  Mark Check ,  Bruce Giamei ,  Timothy Slegel

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/3806

摘要： Disclosed is a method and apparatus providing the capability to prevent particular branches from being written into the BTB, thereby making them non-predictable. By making certain branches only detectable at decode time frame, branch prediction can completely run asynchronous of decode. By allowing branch prediction logic to cover as wide a range of branches as possible, the efficiency of fetching of branch targets way before the branch itself achieves a higher level of precision. This increased level of precision eliminates pipeline stalls between branches and targets where prior concerns of creating data integrity within the pipeline of a microprocessor existed.

摘要翻译： 公开了提供防止特定分支被写入BTB的能力的方法和装置，从而使它们不可预测。 通过使某些分支仅在解码时间帧可检测到，分支预测可以完全执行解码的异步。 通过允许分支预测逻辑覆盖尽可能广泛的分支范围，在分支本身实现更高精度之前，提取分支目标的效率。 这种增加的精度水平消除了分支和目标之间的流水线停顿，其中在微处理器管线内存在创建数据完整性的事先担心。