公开(公告)号：US06966046B2

公开(公告)日：2005-11-15

申请号：US09841505

申请日：2001-04-24

申请人： Brian W. Curran ,  Lisa Bryant Lacey ,  Gregory A. Northrop ,  Ruchir Puri ,  Leon Stok

发明人： Brian W. Curran ,  Lisa Bryant Lacey ,  Gregory A. Northrop ,  Ruchir Puri ,  Leon Stok

IPC分类号： G06F17/50 ,  H01L21/82 ,  H03K19/096 ,  H03K19/20

CPC分类号： G06F17/505

摘要： A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.

摘要翻译： 高性能门库增加了锥形门。 改变堆叠器件的宽度以减少通过一些输入引脚的延迟。 例如在锥形NAND门中，NFET堆叠中的底部器件具有比顶部器件更宽的宽度，以牺牲较大的底部输入到输出引脚延迟为代价来实现较小的顶部输入以输出引脚延迟。 使用合成算法的方法将输入网络修改为栅极引脚连接，并与锥形栅极交换传统的非锥形栅极，以改善时序关键路径的延迟。 最新到达的门输入网络被互换，网络连接到顶针。 然后将栅极转换成锥形栅极，提供通过底栅输入（不是时序关键）的路径。

公开(公告)号：US20090070719A1

公开(公告)日：2009-03-12

申请号：US11853235

申请日：2007-09-11

申请人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri

发明人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.

摘要翻译： 用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。 存储器可以提供逻辑块的延迟对锥形值。 该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。 系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。 锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。

公开(公告)号：US20090070720A1

公开(公告)日：2009-03-12

申请号：US11853276

申请日：2007-09-11

申请人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Lawrence Lange ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri ,  Gebhard Weber

发明人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Lawrence Lange ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri ,  Gebhard Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison.

摘要翻译： 用于识别由于逻辑块变化引起的时序差异的系统，系统可以包括控制器和与控制器通信的存储器。 控制器可以提供先前逻辑块和当前逻辑块的延迟值。 该系统还可以包括一个定时建模器，用于将先前逻辑块的延迟值与用于定时分析的当前逻辑块进行比较。 系统还可以包括基于先前逻辑块和当前逻辑块比较来提供报告的接口。

公开(公告)号：US07676779B2

公开(公告)日：2010-03-09

申请号：US11853235

申请日：2007-09-11

申请人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri

发明人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.

摘要翻译： 用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。 存储器可以提供逻辑块的延迟对锥形值。 该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。 系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。 锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。

公开(公告)号：US08756541B2

公开(公告)日：2014-06-17

申请号：US13431368

申请日：2012-03-27

申请人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Xiaoping Tang ,  Hua Xiang ,  Matthew Mantell Ziegler

发明人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Xiaoping Tang ,  Hua Xiang ,  Matthew Mantell Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/06

摘要： Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.

摘要翻译： 本文提供了相对排序电路合成的系统和方法。 一个方面提供了通过计算设备可访问的至少一个处理器生成至少一个电路设计; 其中产生至少一个电路设计包括：基于至少一个电路设计布局生成至少一个相对顺序结构，所述至少一个相对顺序结构包括与至少一个电路元件相关联的至少一个放置约束; 根据所述至少一个放置约束将与所述至少一个放置约束相关联的所述至少一个电路元件放置在电路设计内; 以及将不与所述至少一个放置约束相关联的电路元件放置在所述电路设计内。 本文还描述了其它实施例和方面。

公开(公告)号：US08365114B2

公开(公告)日：2013-01-29

申请号：US12862838

申请日：2010-08-25

申请人： Eli Arbel ,  David Geiger ,  Victor Kravets ,  Smita Krishnaswamy ,  Ruchir Puri ,  Haoxing Ren

发明人： Eli Arbel ,  David Geiger ,  Victor Kravets ,  Smita Krishnaswamy ,  Ruchir Puri ,  Haoxing Ren

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505

摘要： Two circuits, an original and a modified, are being recognized, with the original circuit having a first logic and the modified circuit having a second logic. The second logic contains at least one desired logic change relative to the first logic. An equivalence line is detected in the original circuit such that the first and second logic are equivalent from the circuit inputs to the equivalence line. At least one point of change is located amongst the logic gates that are neighboring the equivalence line. The points of change are accepted as verified if an observability condition is fulfilled. The observability condition is checked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verified points of change is derived using SAT and Boolean equation solving techniques, in such manner that the first logic becomes equivalent to the second logic.

摘要翻译： 正在识别两个电路，一个原始和一个修改的电路，原始电路具有第一逻辑，并且该修改的电路具有第二逻辑。 第二逻辑包含相对于第一逻辑的至少一个期望的逻辑变化。 在原始电路中检测到等效线，使得第一和第二逻辑等效于从电路输入到等价线。 至少一个变化点位于与等价线相邻的逻辑门之间。 如果可观察性条件得到满足，则可以接受更改点。 可观察性条件在布尔满足度（SAT）公式中进行检查。 通过使用SAT和布尔方程求解技术，使得第一逻辑变为等同于第二逻辑的方式，导出用于验证的变化点的替代逻辑。

公开(公告)号：US20120054699A1

公开(公告)日：2012-03-01

申请号：US12868086

申请日：2010-08-25

申请人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.

摘要翻译： 示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成， 对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

公开(公告)号：US08122400B2

公开(公告)日：2012-02-21

申请号：US12497499

申请日：2009-07-02

申请人： Jeremy T. Hopkins ,  John M. Isakson ,  Joachim Keinert ,  Smita Krishnaswamy ,  Nilesh A. Modi ,  Ruchir Puri ,  Haoxing Ren ,  David L. Rude

发明人： Jeremy T. Hopkins ,  John M. Isakson ,  Joachim Keinert ,  Smita Krishnaswamy ,  Nilesh A. Modi ,  Ruchir Puri ,  Haoxing Ren ,  David L. Rude

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing in between those boundaries a difference circuit representing logic changes.

摘要翻译： 公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。 差分电路表示实现原始电路的修改电路逻辑的变化。 合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和主要输出元件之间没有逻辑改变。 所公开的合成还可以将原始逻辑中的输入侧边界定位成使得原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变。 还公开了一种计算机程序产品。 计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。 计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑的差异电路的变化。

公开(公告)号：US20110004857A1

公开(公告)日：2011-01-06

申请号：US12497499

申请日：2009-07-02

申请人： Jeremy T. Hopkins ,  John M. Isakson ,  Joachim Keinert ,  Smita Krishnaswamy ,  Nilesh A. Modi ,  Ruchir Puri ,  Haoxing Ren ,  David L. Rude

发明人： Jeremy T. Hopkins ,  John M. Isakson ,  Joachim Keinert ,  Smita Krishnaswamy ,  Nilesh A. Modi ,  Ruchir Puri ,  Haoxing Ren ,  David L. Rude

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing inbetween those boundaries a difference circuit representing logic changes.

摘要翻译： 公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。 差分电路表示实现原始电路的修改电路逻辑的变化。 合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和初级输出元件之间没有逻辑改变。 所公开的合成还可以以原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变的方式将原始逻辑中的输入侧边界定位。 还公开了一种计算机程序产品。 计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。 计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑变化的差分电路。

公开(公告)号：US20080281572A1

公开(公告)日：2008-11-13

申请号：US11746709

申请日：2007-05-10

申请人： Ruchir Puri ,  Henry H. K. Tang ,  Kim Yaw Tong

发明人： Ruchir Puri ,  Henry H. K. Tang ,  Kim Yaw Tong

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/16

摘要： A logic design tool, a tool for analyzing soft error sensitivities in logic, and a program product for logic design. A particle generator simulates events likely to occur for a given operating environment. A pre-characterizer provides circuit block responses to simulated events. A circuit response simulator simulates events in a logic design and provides an indication of soft error sensitivity for the design. Based on the soft error sensitivity indication, the design may be modified to reduce the overall soft error sensitivity.

摘要翻译： 逻辑设计工具，用于分析逻辑中的软错误灵敏度的工具，以及用于逻辑设计的程序产品。 粒子发生器模拟给定操作环境可能发生的事件。 预特征化器为模拟事件提供电路块响应。 电路响应仿真器模拟逻辑设计中的事件，并为设计提供软错误灵敏度的指示。 基于软错误灵敏度指示，可以修改设计以降低整体软错误灵敏度。