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    CMOS tapered gate and synthesis method
    1.
    发明授权
    CMOS tapered gate and synthesis method 失效
    CMOS锥形栅极及其合成方法

    公开(公告)号：US06966046B2

    公开(公告)日：2005-11-15

    申请号：US09841505

    申请日：2001-04-24

    申请人： Brian W. Curran ,  Lisa Bryant Lacey ,  Gregory A. Northrop ,  Ruchir Puri ,  Leon Stok

    发明人： Brian W. Curran ,  Lisa Bryant Lacey ,  Gregory A. Northrop ,  Ruchir Puri ,  Leon Stok

    IPC分类号： G06F17/50 ,  H01L21/82 ,  H03K19/096 ,  H03K19/20

    CPC分类号： G06F17/505

    摘要： A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.

    摘要翻译： 高性能门库增加了锥形门。 改变堆叠器件的宽度以减少通过一些输入引脚的延迟。 例如在锥形NAND门中，NFET堆叠中的底部器件具有比顶部器件更宽的宽度，以牺牲较大的底部输入到输出引脚延迟为代价来实现较小的顶部输入以输出引脚延迟。 使用合成算法的方法将输入网络修改为栅极引脚连接，并与锥形栅极交换传统的非锥形栅极，以改善时序关键路径的延迟。 最新到达的门输入网络被互换，网络连接到顶针。 然后将栅极转换成锥形栅极，提供通过底栅输入（不是时序关键）的路径。

    Logic Block Timing Estimation Using Conesize
    2.
    发明申请
    Logic Block Timing Estimation Using Conesize 有权
    使用锥形的逻辑块时序估计

    公开(公告)号：US20090070719A1

    公开(公告)日：2009-03-12

    申请号：US11853235

    申请日：2007-09-11

    申请人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri

    发明人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.

    摘要翻译： 用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。 存储器可以提供逻辑块的延迟对锥形值。 该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。 系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。 锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。

    Logic block timing estimation using conesize
    4.
    发明授权
    Logic block timing estimation using conesize 有权
    使用锥形的逻辑块定时估计

    公开(公告)号：US07676779B2

    公开(公告)日：2010-03-09

    申请号：US11853235

    申请日：2007-09-11

    申请人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri

    发明人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.

    摘要翻译： 用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。 存储器可以提供逻辑块的延迟对锥形值。 该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。 系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。 锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。

    Method and apparatus for reducing bus noise and power consumption
    5.
    发明授权
    Method and apparatus for reducing bus noise and power consumption 失效
    降低总线噪声和功耗的方法和装置

    公开(公告)号：US5572736A

    公开(公告)日：1996-11-05

    申请号：US414554

    申请日：1995-03-31

    申请人： Brian W. Curran

    发明人： Brian W. Curran

    IPC分类号： G06F13/40 ,  G06F1/32

    CPC分类号： G06F13/4072 ,  Y02B60/1228 ,  Y02B60/1235

    摘要： In a computer system comprising a plurality of subsystems, interconnected by a bus comprising bit drivers and bit receivers, data words are transmitted on the bus in the form of code words. The code words are formulated such that the number of bits of the bus which changes with the transmission of successive code words is minimized. A switching code, comprising one or more bits, defines a plurality of mapping codes and a data word to be transmitted is mapped by use of the mapping codes to a plurality of code words. One of the plurality of code words differing from a previously transmitted code word in the least number of bit positions is selected. The selected code words is transmitted, together with a switching code, identifying the mapping from which the transmitted code word was generated. At the receiving end of the bus, the switching code is decoded to identify the mapping used in creating the code word. Using the identified mapping, the original data word is recovered.

    摘要翻译： 在包括由包括位驱动器和位接收器的总线互连的多个子系统的计算机系统中，数据字以代码字的形式在总线上传送。 编码字被配置为使得随着连续代码字的传输而变化的总线的位数最小化。 包括一个或多个位的切换代码定义多个映射代码，并且将要发送的数据字通过使用映射代码映射到多个代码字。 选择与最少数量的位位置中的先前发送的代码字不同的多个代码字中的一个。 所选择的代码字与切换代码一起发送，识别生成发送的代码字的映射。 在总线的接收端，对切换代码进行解码以识别用于创建代码字的映射。 使用识别的映射，恢复原始数据字。

    Expandable memory having plural memory cards for distributively storing system data
    7.
    发明授权
    Expandable memory having plural memory cards for distributively storing system data 失效
    可扩展存储器，具有用于分布式存储系统数据的多个存储卡

    公开(公告)号：US5428762A

    公开(公告)日：1995-06-27

    申请号：US850194

    申请日：1992-03-11

    申请人： Brian W. Curran ,  Joseph L. Temple, III

    发明人： Brian W. Curran ,  Joseph L. Temple, III

    IPC分类号： G11C5/00 ,  G06F13/16 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

    CPC分类号： G06F13/1694

    摘要： An improved memory system and memory controller which permits simplified memory upgrades in the field. The system includes a memory board with multiple card sockets. As additional cards are added the data cables are distributed among the cards and the memory controller is programmed to coordinate the sequencing of the memory in the cards. Data is transferred between the cards and memory controller via distributively coupled cables. Control and address signals are provided to cards via wires embedded in the memory board from the memory controller. A repowering circuit on each card makes copies of the control and address signals which are sent to other cards through the embedded wires in the board. Data received by a card is stored in memory through steering logic and buffers.

    摘要翻译： 改进的存储器系统和存储器控制器，其允许在现场简化存储器升级。 该系统包括一个具有多个卡插槽的存储器板。 随着附加卡被添加，数据电缆分布在卡之间，并且存储器控制器被编程以协调卡中的存储器的排序。 数据通过分布式耦合电缆在卡和存储控制器之间传输。 控制和地址信号通过从存储器控制器嵌入存储器板中的线路提供给卡。 每个卡上的重新加电电路将通过板中的嵌入式电线发送到其他卡的控制和地址信号的副本。 由卡接收的数据通过转向逻辑和缓冲器存储在存储器中。

    Method and circuit for reading and writing an instruction buffer
    9.
    发明授权
    Method and circuit for reading and writing an instruction buffer 有权
    用于读写指令缓冲器的方法和电路

    公开(公告)号：US07243170B2

    公开(公告)日：2007-07-10

    申请号：US10707149

    申请日：2003-11-24

    申请人： Taqi N. Buti ,  Brian W. Curran ,  Maureen A. Delaney ,  Saiful Islam ,  Zakaria M. Khwaja ,  Jafar Nahidi ,  Dung Q. Nguyen

    发明人： Taqi N. Buti ,  Brian W. Curran ,  Maureen A. Delaney ,  Saiful Islam ,  Zakaria M. Khwaja ,  Jafar Nahidi ,  Dung Q. Nguyen

    IPC分类号： G06F3/00 ,  G06F5/00

    CPC分类号： G06F9/3802 ,  G06F9/3814

    摘要： An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction

    摘要翻译： 指令缓冲器和缓冲指令的方法。 所述指令缓冲器包括：分割成从第一存储器子阵列到最后存储器子阵列的顺序排列的多个相同的存储器子阵列的存储器阵列，每个存储器子阵列具有多个指令条目位置，并且适于存储 任何一个存储器子阵列的单个指令输入位置中的一组并行指令的不同指令，以从第一指令到最后指令的顺序排列的并发指令集

    Low power overdriven pass gate latch
    10.
    发明授权
    Low power overdriven pass gate latch 失效
    低功耗过驱闸闸

    公开(公告)号：US06882205B2

    公开(公告)日：2005-04-19

    申请号：US10290636

    申请日：2002-11-08

    申请人： Brian W. Curran ,  Edward T. Malley

    发明人： Brian W. Curran ,  Edward T. Malley

    IPC分类号： G06F1/04 ,  G06F1/32

    CPC分类号： G06F1/32 ,  G06F1/04

    摘要： A clocking circuit decreases the load on the local clock signals to save power. The load is decreased by altering the structure of the latches. Typically, a passgate style latch is used where both an NFET and a PFET are used to control dataflow. Here, the PFET has been removed and the load is decreased. However, it is difficult to pass a logical 1 through an NFET and this increases both the rising slew and rising edge delay through the latch. The effect is mitigated, though, by overdriving the local clock block (LCB) local clocks to drive a local clock to the latches by passgates using only NFET transistors in the master latches and slave latches. Overdrivig the NFET gate allows the NFET to pass a full-level logical 1 signal.

    摘要翻译： 时钟电路减少本地时钟信号的负载，以节省功耗。 通过改变锁存器的结构来减小负载。 通常，使用通道式锁存器，其中NFET和PFET都用于控制数据流。 这里，PFET被去除并且负载减小。 然而，难以通过NFET传递逻辑1，并且通过锁存器增加上升的转换和上升沿延迟。 尽管如此，通过过驱动本地时钟块（LCB）本地时钟来驱动本地时钟到本地时钟，通过在主锁存器和从锁存器中仅使用NFET晶体管的通道来减轻效果。 过压NFET门允许NFET通过全电平逻辑1信号。