利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.021 秒)

    INTEGRATED CIRCUIT (IC) DESIGN METHOD AND METHOD OF ANALYZING RADIATION-INDUCED SINGLE-EVENT UPSETS IN CMOS LOGIC DESIGNS
    1.
    发明申请
    INTEGRATED CIRCUIT (IC) DESIGN METHOD AND METHOD OF ANALYZING RADIATION-INDUCED SINGLE-EVENT UPSETS IN CMOS LOGIC DESIGNS 审中-公开
    集成电路（IC）设计方法和分析CMOS逻辑设计中辐射诱导的单事件的方法

    公开(公告)号：US20080281572A1

    公开(公告)日：2008-11-13

    申请号：US11746709

    申请日：2007-05-10

    申请人： Ruchir Puri ,  Henry H. K. Tang ,  Kim Yaw Tong

    发明人： Ruchir Puri ,  Henry H. K. Tang ,  Kim Yaw Tong

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G06F2217/16

    摘要： A logic design tool, a tool for analyzing soft error sensitivities in logic, and a program product for logic design. A particle generator simulates events likely to occur for a given operating environment. A pre-characterizer provides circuit block responses to simulated events. A circuit response simulator simulates events in a logic design and provides an indication of soft error sensitivity for the design. Based on the soft error sensitivity indication, the design may be modified to reduce the overall soft error sensitivity.

    摘要翻译： 逻辑设计工具，用于分析逻辑中的软错误灵敏度的工具，以及用于逻辑设计的程序产品。 粒子发生器模拟给定操作环境可能发生的事件。 预特征化器为模拟事件提供电路块响应。 电路响应仿真器模拟逻辑设计中的事件，并为设计提供软错误灵敏度的指示。 基于软错误灵敏度指示，可以修改设计以降低整体软错误灵敏度。

    METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING
    3.
    发明申请
    METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING 有权
    用于加速软错误测试的方法和结构

    公开(公告)号：US20090065955A1

    公开(公告)日：2009-03-12

    申请号：US11852353

    申请日：2007-09-10

    申请人： Michael S. Gordon ,  Kenneth P. Rodbell ,  Henry H. K. Tang

    发明人： Michael S. Gordon ,  Kenneth P. Rodbell ,  Henry H. K. Tang

    IPC分类号： H01L23/48 ,  G01R31/26 ,  H01L21/4763

    CPC分类号： G01R31/2881 ,  G01R31/2858 ,  G01R31/31816 ,  H01L21/76825 ,  H01L21/84 ,  H01L23/53233 ,  H01L23/53238 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms.

    摘要翻译： 一种集成电路，形成集成电路的方法以及用于软错误的集成电路测试的方法失败。 集成电路包括：硅衬底; 形成在所述基板上的电介质层; 形成在电介质层中的导电线，将形成在基板中的半导体器件互连成电路的导线; 以及靠近一个或多个半导体器件的集成电路芯片中的α粒子发射区域。 该方法包括将集成电路暴露于热中子的人造通量，以使α粒子发射区中的原子裂变为α粒子和其它原子。

    Optimization of storage and power consumption with soft error predictor-corrector
    4.
    发明授权
    Optimization of storage and power consumption with soft error predictor-corrector 失效
    使用软错误预测器校正器优化存储和功耗

    公开(公告)号：US06986078B2

    公开(公告)日：2006-01-10

    申请号：US10213690

    申请日：2002-08-07

    申请人： Kenneth P. Rodbell ,  Henry H. K. Tang ,  Robert M. Trepp ,  Robert Chi-Foon Wong

    发明人： Kenneth P. Rodbell ,  Henry H. K. Tang ,  Robert M. Trepp ,  Robert Chi-Foon Wong

    IPC分类号： G06F11/00

    CPC分类号： H04L1/0001

    摘要： A method and system for mitigating the impact of radiation induced in a data processor incorporating integrated circuits. The method comprises the steps of determining the location of the data processor, determining a set of radiation sources and intensities at that location, and estimating the soft error rate of the data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value. The data processor is modified (either hardware or software) in response to the estimate value at times the estimate value exceeds a predetermined value.

    摘要翻译： 一种用于减轻包含集成电路的数据处理器中引起的辐射影响的方法和系统。 该方法包括以下步骤：确定数据处理器的位置，确定该位置处的一组辐射源和强度，以及根据确定的所述集成的辐射强度和几何特性来估计数据处理器的软错误率 电路提供估计值。 数据处理器在估计值超过预定值的时候响应于估计值被修改（硬件或软件）。

    Method and structures for accelerated soft-error testing
    7.
    发明授权
    Method and structures for accelerated soft-error testing 有权
    加速软错误测试的方法和结构

    公开(公告)号：US07939823B2

    公开(公告)日：2011-05-10

    申请号：US11852353

    申请日：2007-09-10

    申请人： Michael S. Gordon ,  Kenneth P. Rodbell ,  Henry H. K. Tang

    发明人： Michael S. Gordon ,  Kenneth P. Rodbell ,  Henry H. K. Tang

    IPC分类号： H01L23/58 ,  H01L21/00

    CPC分类号： G01R31/2881 ,  G01R31/2858 ,  G01R31/31816 ,  H01L21/76825 ,  H01L21/84 ,  H01L23/53233 ,  H01L23/53238 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms.

    摘要翻译： 一种集成电路，形成集成电路的方法以及用于软错误的集成电路测试的方法失败。 集成电路包括：硅衬底; 形成在所述基板上的电介质层; 形成在电介质层中的导电布线，将形成在基板中的半导体器件互连到电路中的导线; 以及靠近一个或多个半导体器件的集成电路芯片中的α粒子发射区域。 该方法包括将集成电路暴露于热中子的人造通量，以使α粒子发射区中的原子裂变为α粒子和其它原子。