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    DISTRIBUTED AVERAGING ANALOG TO DIGITAL CONVERTER TOPOLOGY
    1.
    发明申请
    DISTRIBUTED AVERAGING ANALOG TO DIGITAL CONVERTER TOPOLOGY 有权
    分布式平均模拟到数字转换器拓扑学

    公开(公告)号：US20030218560A1

    公开(公告)日：2003-11-27

    申请号：US10460622

    申请日：2003-06-13

    Applicant: Broadcom Corporation

    Inventor： Jan Mulder ,  Christopher Michael Ward

    IPC: H03M001/36

    CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

    Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

    Abstract translation: 模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个 第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。

    SUBRANGING ANALOG TO DIGITAL CONVERTER WITH MULTI-PHASE CLOCK TIMING
    2.
    发明申请
    SUBRANGING ANALOG TO DIGITAL CONVERTER WITH MULTI-PHASE CLOCK TIMING 有权
    将数字转换器与多相时钟时序相结合

    公开(公告)号：US20030218556A1

    公开(公告)日：2003-11-27

    申请号：US10359201

    申请日：2003-02-06

    Applicant: Broadcom Corporation

    Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

    IPC: H03M001/12

    CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

    Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

    Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

    Subranging analog to digital converter with multi-phase clock timing
    3.
    发明申请
    Subranging analog to digital converter with multi-phase clock timing 有权
    使用多相时钟定时将模数转换器分段

    公开(公告)号：US20040155807A1

    公开(公告)日：2004-08-12

    申请号：US10625702

    申请日：2003-07-24

    Applicant: Broadcom Corporation

    Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

    IPC: H03M001/12

    CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

    Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output ofthe coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

    Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 基准梯形图，其基于粗略ADC放大器的输出由精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出， 其中精细电容器在第一时钟相位期间连接到电压子范围，在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为N-bi t输出。

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