Abstract:
An Analog to Digital Converter (ADC) includes an ADC core, a first switched capacitor voltage regulator, and a second switched capacitor voltage regulator. The ADC core includes a plurality of digital components that sample an incoming signal based on an ADC clock, a first voltage, and a first ground and a plurality of analog components configured to operate using a second voltage and a second ground. The first switched capacitor voltage regulator produces the first voltage and the first ground for the plurality of digital components using a supply voltage, a supply ground, and the ADC clock. The second switched capacitor voltage regulator produces the second voltage and the second ground using the supply voltage, the supply ground, and the ADC clock. Switching of the first and second switched capacitor voltage regulators is performed using complementary and non-overlapping clocks having switching frequency that is based upon the ADC clock.
Abstract:
Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fall. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).
Abstract:
An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD3, SDFR, and IM3 measures.
Abstract:
A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.
Abstract:
A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.
Abstract:
Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fail. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).