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1.发明授权Method and apparatus for excess loop delay compensation in continuous-time sigma-delta analog-to-digital converters 有权连续时间Σ-Δ模数转换器中多余环路延迟补偿的方法和装置公开(公告)号：US09577662B2
公开(公告)日：2017-02-21
申请号：US14954532
申请日：2015-11-30
Applicant: Broadcom Corporation
Inventor： Guowen Wei , Xinyu Yu , Michael Inerfield , Tom Kwan
CPC classification number: H03M3/37 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/144 , H03M1/466 , H03M1/804 , H03M3/426
Abstract: A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.
Abstract translation: 本公开的CT-SDADC将模拟输入信号从模拟信号域中的表示转换为数字信号域中的表示以提供数字输出信号。 CT-SDADC通过在SAR子ADC中的两相之间切换实现模数转换和ELDC：采样阶段和转换阶段。 在采样阶段，SAR sub-ADC捕获多个可切换电容阵列上的模拟输入信号。 转换阶段包括多个步骤，并且数字输出信号的一个或多个位在转换阶段的每个步骤被解析。 在转换阶段，SC-DAC的一部分由延迟的CT-SDADC输出驱动，以有效地补偿由CT-SDADC反馈回路引起的多余的环路延迟。
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2.发明申请Method and Apparatus for Excess Loop Delay Compensation in Continuous-Time Sigma-Delta Analog-to-Digital Converters 有权连续时间Σ-Delta模数转换器中循环延迟补偿的方法和装置公开(公告)号：US20160233872A1
公开(公告)日：2016-08-11
申请号：US14954532
申请日：2015-11-30
Applicant: BROADCOM CORPORATION
Inventor： Guowen WEI , Xinyu Yu , Michael Inerfield , Tom Kwan
CPC classification number: H03M3/37 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/144 , H03M1/466 , H03M1/804 , H03M3/426
Abstract: A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.
Abstract translation: 本公开的CT-SDADC将模拟输入信号从模拟信号域中的表示转换为数字信号域中的表示以提供数字输出信号。 CT-SDADC通过在SAR子ADC中的两相之间切换实现模数转换和ELDC：采样阶段和转换阶段。 在采样阶段，SAR sub-ADC捕获多个可切换电容阵列上的模拟输入信号。 转换阶段包括多个步骤，并且数字输出信号的一个或多个位在转换阶段的每个步骤被解析。 在转换阶段，SC-DAC的一部分由延迟的CT-SDADC输出驱动，以有效地补偿由CT-SDADC反馈回路引起的多余的环路延迟。
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