公开(公告)号：US09304950B2

公开(公告)日：2016-04-05

申请号：US13628067

申请日：2012-09-27

Applicant: Broadcom Corporation

Inventor： Velu Pillai ,  Vivek Telang

IPC: G06F13/14 ,  G06F13/40 ,  H04L12/40 ,  H04L25/00 ,  H04L29/06 ,  H04L25/49

CPC classification number: H04L7/0091 ,  G06F13/14 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4286 ,  H04L1/0042 ,  H04L1/0047 ,  H04L7/0087 ,  H04L12/40 ,  H04L25/00 ,  H04L25/4906 ,  H04L69/08 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract translation: 与100 GBASE背板一起使用的PHY芯片的系统侧接口使用NRZ信号格式发送和接收数据，但数据速率约为26.5 Gbps /每通道到27.2 Gbps /每通道，这是一致的 与PAM 4信令协议。 因此，PHY芯片与开关或控制器芯片之间的芯片到芯片通信可以使用“超频”NRZ信号格式，减少所需的逻辑量，从而降低信号延迟，并降低芯片面积和功率 实现逻辑所需的消费。

公开(公告)号：US20140064088A1

公开(公告)日：2014-03-06

申请号：US14075113

申请日：2013-11-08

Applicant: Broadcom Corporation

Inventor： Ali Ghiasi ,  Velu Pillai ,  Sundar Chidambara

IPC: H04L12/801

CPC classification number: H04L47/10 ,  H04L7/041 ,  H04L49/60

Abstract: A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox.

Abstract translation: 一种用于增加网络交换机中输入/输出速度的系统和方法。 提供了一种物理层设备，其包括将数据流标识符插入到提供给齿轮箱的数据流的物理编码子层。 在一个实施例中，齿轮箱是5至2变速箱，其可以将较窄接口上的10G / 40G数据流的各种组合传送到具有逆变速箱的第二物理层装置。

公开(公告)号：US20130268783A1

公开(公告)日：2013-10-10

申请号：US13628120

申请日：2012-09-27

Applicant: BROADCOM CORPORATION

Inventor： Wael William Diab ,  Velu Pillai

IPC: G06F1/32

CPC classification number: H04L12/12 ,  Y02D30/30

Abstract: A system and method for using energy efficiency network refresh signals for exchanging link partner and device information. Energy savings can be realized through a usage of a energy saving state such as a low power idle (LPI) mode. In one embodiment, refresh signals used during the LPI mode can be used to encode information or state within the refresh signals. In general, such encoded information enables link partners to exchange information that would otherwise need to wait until the link partners have transitioned from an energy saving state back to the active state. In various examples, the messaging during the energy saving state can be used to facilitate synchronization during the energy saving state, transitions from the energy saving state, etc.

Abstract translation: 一种使用能效网络刷新信号来交换链路伙伴和设备信息的系统和方法。 通过使用诸如低功率空闲（LPI）模式的节能状态可以实现节能。 在一个实施例中，在LPI模式期间使用的刷新信号可用于对刷新信号内的信息或状态进行编码。 通常，这样的编码信息使得链路伙伴能够交换否则需要等待的链接伙伴已经从节能状态转换到活动状态的信息。 在各种示例中，节能状态期间的消息传递可以用于促进节能状态期间的同步，从节能状态转变等

公开(公告)号：US10069620B2

公开(公告)日：2018-09-04

申请号：US15082204

申请日：2016-03-28

Applicant: BROADCOM CORPORATION

Inventor： Velu Pillai ,  Vivek Telang

IPC: G06F13/14 ,  H04L7/00 ,  G06F13/40 ,  H04L12/40 ,  H04L25/00 ,  H04L29/06 ,  G06F13/42 ,  H04L1/00 ,  H04L25/49

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

公开(公告)号：US20140075076A1

公开(公告)日：2014-03-13

申请号：US13628067

申请日：2012-09-27

Applicant: BROADCOM CORPORATION

Inventor： Velu Pillai ,  Vivek Telang

IPC: G06F13/14

CPC classification number: H04L7/0091 ,  G06F13/14 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4286 ,  H04L1/0042 ,  H04L1/0047 ,  H04L7/0087 ,  H04L12/40 ,  H04L25/00 ,  H04L25/4906 ,  H04L69/08 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract translation: 与100GBASE背板一起使用的PHY芯片的系统侧接口使用NRZ信号格式发送和接收数据，但数据速率约为26.5 Gbps /每通道到27.2 Gbps /每通道，这与 PAM 4信令协议。 因此，PHY芯片与开关或控制器芯片之间的芯片到芯片通信可以使用“超频”NRZ信号格式，减少所需的逻辑量，从而降低信号延迟，并降低芯片面积和功率 实现逻辑所需的消费。

公开(公告)号：US20160211966A1

公开(公告)日：2016-07-21

申请号：US15082204

申请日：2016-03-28

Applicant: BROADCOM CORPORATION

Inventor： Velu Pillai ,  Vivek Telang

IPC: H04L7/00 ,  G06F13/42 ,  H04L1/00 ,  G06F13/40

CPC classification number: H04L7/0091 ,  G06F13/14 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4286 ,  H04L1/0042 ,  H04L1/0047 ,  H04L7/0087 ,  H04L12/40 ,  H04L25/00 ,  H04L25/4906 ,  H04L69/08 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract translation: 与100GBASE背板一起使用的PHY芯片的系统侧接口使用NRZ信号格式发送和接收数据，但数据速率约为26.5 Gbps /每通道到27.2 Gbps /每通道，这与 PAM 4信令协议。 因此，PHY芯片与开关或控制器芯片之间的芯片到芯片通信可以使用“超频”NRZ信号格式，减少所需的逻辑量，从而降低信号延迟，并降低芯片面积和功率 实现逻辑所需的消费。

公开(公告)号：US09130851B2

公开(公告)日：2015-09-08

申请号：US14075113

申请日：2013-11-08

Applicant: Broadcom Corporation

Inventor： Ali Ghiasi ,  Velu Pillai ,  Sundar Chidambara

IPC: H04L12/801 ,  H04L7/04 ,  H04L12/931

CPC classification number: H04L47/10 ,  H04L7/041 ,  H04L49/60

Abstract: A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox.

Abstract translation: 一种用于增加网络交换机中输入/输出速度的系统和方法。 提供了一种物理层设备，其包括将数据流标识符插入到提供给齿轮箱的数据流的物理编码子层。 在一个实施例中，齿轮箱是5至2变速箱，其可以将较窄接口上的10G / 40G数据流的各种组合传送到具有逆变速箱的第二物理层装置。