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公开(公告)号：US09304950B2
公开(公告)日：2016-04-05
申请号：US13628067
申请日：2012-09-27
Applicant: Broadcom Corporation
Inventor： Velu Pillai , Vivek Telang
CPC classification number: H04L7/0091 , G06F13/14 , G06F13/4022 , G06F13/4072 , G06F13/4286 , H04L1/0042 , H04L1/0047 , H04L7/0087 , H04L12/40 , H04L25/00 , H04L25/4906 , H04L69/08 , Y02D10/14 , Y02D10/151
Abstract: A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.
Abstract translation: 与100 GBASE背板一起使用的PHY芯片的系统侧接口使用NRZ信号格式发送和接收数据，但数据速率约为26.5 Gbps /每通道到27.2 Gbps /每通道，这是一致的 与PAM 4信令协议。 因此，PHY芯片与开关或控制器芯片之间的芯片到芯片通信可以使用“超频”NRZ信号格式，减少所需的逻辑量，从而降低信号延迟，并降低芯片面积和功率 实现逻辑所需的消费。
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2.发明申请公开(公告)号：US20150146766A1
公开(公告)日：2015-05-28
申请号：US14614829
申请日：2015-02-05
Applicant: BROADCOM CORPORATION
Inventor： Lorenzo Longo , Vivek Telang
CPC classification number: H04L25/4917 , H04L25/03057 , H04L25/03885 , H04L27/02
Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.
Abstract translation: 短距离通信系统包括多个通信SERDES，其通过短距离信道介质传送数据，例如位于公共PCB上的码片之间的背板连接（例如，PCB轨迹）。 生成多级调制数据信号以通过短距离信道介质发送/接收数据。 诸如四电平PAM的多电平调制数据信号降低数据信号速率，从而降低插入损耗，功率，电路的复杂性以及所需的芯片空间。
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公开(公告)号：US20130121391A1
公开(公告)日：2013-05-16
申请号：US13734619
申请日：2013-01-04
Applicant: Broadcom Corporation
Inventor： Namik Kemal Kocaman , Afshin Momtaz , Velu Chellam Pillai , Vivek Telang , Sundararajan Chidambara , Magesh Valliappan
IPC: H04B17/00
CPC classification number: H04B17/21 , H03F3/195 , H03F2200/375 , H03F2200/405 , H04L25/03019 , H04L27/08
Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.
Abstract translation: 公开了一种用于补偿通信信号中的一个或多个偏移的装置和方法。 通信接收机可以执行偏移调整算法来补偿一个或多个偏移。 初始搜索过程从一个或多个偏移调整校正确定一个或多个所选择的偏移调整校正的一个或多个信号度量图。 偏移调整算法基于一个或多个信号映射确定一个或多个所选偏移调整校正的一个或多个最优点。 自适应偏移算法将一个或多个所选择的偏移调整校正中的每一个调整到其各自的最佳点和/或一个或多个未选择的偏移调整校正中的每一个，以适应多个可能的偏移校正中的对应的一个，以提供一个或多个 调整后的偏移调整校正。 跟踪模式过程优化一个或多个经调整的偏移调整校正。
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公开(公告)号：US10069620B2
公开(公告)日：2018-09-04
申请号：US15082204
申请日：2016-03-28
Applicant: BROADCOM CORPORATION
Inventor： Velu Pillai , Vivek Telang
IPC: G06F13/14 , H04L7/00 , G06F13/40 , H04L12/40 , H04L25/00 , H04L29/06 , G06F13/42 , H04L1/00 , H04L25/49
Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.
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Patent Agency Ranking
公开(公告)号：US09338040B2
公开(公告)日：2016-05-10
申请号：US14614829
申请日：2015-02-05
Applicant: BROADCOM CORPORATION
Inventor： Lorenzo Longo , Vivek Telang
CPC classification number: H04L25/4917 , H04L25/03057 , H04L25/03885 , H04L27/02
Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.
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公开(公告)号：US20130243072A1
公开(公告)日：2013-09-19
申请号：US13871831
申请日：2013-04-26
Applicant: BROADCOM CORPORATION
Inventor： Vivek Telang , Hong Chen , Vasudevan Parthasarathy , Jun Cao , Afshin Momtaz , Ali Ghiasi , Chung-Jue Chen
IPC: H04L27/00
CPC classification number: H04L27/0002 , H04B1/0007 , H04B1/406
Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.
Abstract translation: 根据示例性实施例，通信接收机可以包括被配置为放大接收信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到所述接收信号的输出的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作 。
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公开(公告)号：US20160211966A1
公开(公告)日：2016-07-21
申请号：US15082204
申请日：2016-03-28
Applicant: BROADCOM CORPORATION
Inventor： Velu Pillai , Vivek Telang
CPC classification number: H04L7/0091 , G06F13/14 , G06F13/4022 , G06F13/4072 , G06F13/4286 , H04L1/0042 , H04L1/0047 , H04L7/0087 , H04L12/40 , H04L25/00 , H04L25/4906 , H04L69/08 , Y02D10/14 , Y02D10/151
Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.
Abstract translation: 与100GBASE背板一起使用的PHY芯片的系统侧接口使用NRZ信号格式发送和接收数据，但数据速率约为26.5 Gbps /每通道到27.2 Gbps /每通道，这与 PAM 4信令协议。 因此，PHY芯片与开关或控制器芯片之间的芯片到芯片通信可以使用“超频”NRZ信号格式，减少所需的逻辑量，从而降低信号延迟，并降低芯片面积和功率 实现逻辑所需的消费。
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公开(公告)号：US08948237B2
公开(公告)日：2015-02-03
申请号：US13734619
申请日：2013-01-04
Applicant: Broadcom Corporation
Inventor： Namik Kemal Kocaman , Afshin Momtaz , Velu Chellam Pillai , Vivek Telang , Sundararajan Chidambara , Magesh Valliappan
CPC classification number: H04B17/21 , H03F3/195 , H03F2200/375 , H03F2200/405 , H04L25/03019 , H04L27/08
Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.
Abstract translation: 公开了一种用于补偿通信信号中的一个或多个偏移的装置和方法。 通信接收机可以执行偏移调整算法来补偿一个或多个偏移。 初始搜索过程从一个或多个偏移调整校正确定一个或多个所选择的偏移调整校正的一个或多个信号度量图。 偏移调整算法基于一个或多个信号映射确定一个或多个所选偏移调整校正的一个或多个最优点。 自适应偏移算法将一个或多个所选择的偏移调整校正中的每一个调整到它们各自的最佳点和/或一个或多个未选择的偏移调整校正中的每一个到多个可能的偏移校正中的对应的一个，以提供一个或多个 调整后的偏移调整校正。 跟踪模式过程优化一个或多个经调整的偏移调整校正。
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公开(公告)号：US20140075076A1
公开(公告)日：2014-03-13
申请号：US13628067
申请日：2012-09-27
Applicant: BROADCOM CORPORATION
Inventor： Velu Pillai , Vivek Telang
IPC: G06F13/14
CPC classification number: H04L7/0091 , G06F13/14 , G06F13/4022 , G06F13/4072 , G06F13/4286 , H04L1/0042 , H04L1/0047 , H04L7/0087 , H04L12/40 , H04L25/00 , H04L25/4906 , H04L69/08 , Y02D10/14 , Y02D10/151
Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.
Abstract translation: 与100GBASE背板一起使用的PHY芯片的系统侧接口使用NRZ信号格式发送和接收数据，但数据速率约为26.5 Gbps /每通道到27.2 Gbps /每通道，这与 PAM 4信令协议。 因此，PHY芯片与开关或控制器芯片之间的芯片到芯片通信可以使用“超频”NRZ信号格式，减少所需的逻辑量，从而降低信号延迟，并降低芯片面积和功率 实现逻辑所需的消费。
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